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mypro_synfifo
基于IP核RAM的同步fifo设计,工程使用Xilinx的开发软件ISE(RAM-based synchronization fifo IP core design, engineering, software development using Xilinx ISE)
- 2020-09-22 01:27:56下载
- 积分:1
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FIR
FIR滤波器的VHDL源代码及测试文件,已通过编译仿真,绝对正确。(FIR filter VHDL source code and test files, has passed the compiled simulation, absolutely correct.)
- 2021-04-15 11:08:54下载
- 积分:1
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LaurentCPM
Laurent程序,用于CPM信号的调制,接收和分解,译码,以及判断(Laurent procedures for CPM modulation of the signal, and decomposition receiving, decoding, and to determine)
- 2013-08-16 01:32:40下载
- 积分:1
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程序
传感器是一种检测装置,能感受到被测量的信息,并能将感受到的信息,按一定规律变换成为电信号或其他所需形式的信息输出,以满足信息的传输、处理、存储、显示、记录和控制等要求(Sensor is a kind of detection device, which can sense the measured information and transform it into electrical signal or other required information output according to certain rules to meet the requirements of information transmission, processing, storage, display, recording and control.)
- 2020-06-18 22:00:01下载
- 积分:1
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rs-codec-8-16
RS[255,223]纠错码verilog源码,包含编码和解码模块,以及testbench等。(Verilog source code for RS[255,223] encoder and decoder, with testbench included.)
- 2021-04-28 15:58:44下载
- 积分:1
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EDA
十进制计算机,实现十进制计数功能,简单可靠(vhdl)
- 2009-12-26 21:45:43下载
- 积分:1
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my_lms
自适应滤波,对输入信号进行选择性的加权处理,使输出达到最优化,并且能够跟踪和适应系统和环境的动态变化(Least mean square,of the input signal processing, selective weighted output, and optimize can track and adapt to the dynamic changes of the system and environment)
- 2010-10-14 15:30:00下载
- 积分:1
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uart
UART串口的verilog源代码,完全正确...........(UART serial Verilog source code, completely correct ...........)
- 2009-03-02 14:44:16下载
- 积分:1
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一篇用VHDL实现快速傅立叶变换的论文
一篇用VHDL实现快速傅立叶变换的论文,包括原理分析和代码实现,印度圣雄甘地大学M.A.学院提供(VHDL with a Fast Fourier Transform papers, including the principle of analysis and implementation of the code, the Mahatma Gandhi Institute of the University of Marat)
- 2004-10-05 11:06:01下载
- 积分:1
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singlecycle_mips
single cycle mips design by verilog.
- 2020-09-07 19:48:02下载
- 积分:1