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REMOTE
orcad schematics for 8051 with rtc and lcd
- 2011-12-01 07:11:52下载
- 积分：1
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PLL
FPGA板上的锁存器PLL控制代码（verilog代码）(FPGA board latch the PLL control code (Verilog code))
- 2021-03-19 17:29:19下载
- 积分：1
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为验证系统的Verilog设计
System Verilog for design verification
- 2022-02-11 21:30:00下载
- 积分：1
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UART
A simple preoteus based design to display the characters typed int the keyboard into LCD using UART of 8051.Plz make sure that TTL to RS232 is inserted in between the microcontroller and virtual terminal which is not shown in the design.
- 2009-12-24 00:04:13下载
- 积分：1
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scramble
基于VHDL实现加扰器解扰器的设计，与仿真。(VHDL-based scrambler descrambler design and simulation.)
- 2013-01-11 20:15:54下载
- 积分：1
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这是一个HDB3的译码器，实现从HDB3双极性码到高低电平二值序列的转化...
这是一个HDB3的译码器，实现从HDB3双极性码到高低电平二值序列的转化-This is a decoder of the HDB3, HDB3 bipolar from high-low-level code to the conversion of binary sequences
- 2022-03-23 10:36:34下载
- 积分：1
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参数化FFT源代码，点数和位宽可变，内附testbench和说明文档
参数化FFT源代码，点数和位宽可变，内附testbench和说明文档-parameters of the source code FFT, counting and variable bit-enclosing testbench and documentation
- 2022-02-20 03:06:01下载
- 积分：1
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VHDLman
VHDL book for reference
- 2010-01-18 17:40:26下载
- 积分：1
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chenxu
电子时钟，可以显示四位，两位显示分钟，两位显示秒，可以用按键控制清零，以及加减数(Electronic clock, you can display four bit, two bit display minutes, the second display seconds, can be used to control the key to clear, and the addition of subtraction)
- 2017-04-22 21:29:14下载
- 积分：1
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add
流水线乘法器与加法器
开发环境：Modelsim（verilog hdl）(Multiplier and adder pipeline development environment: Modelsim (verilog hdl))
- 2009-05-18 12:19:24下载
- 积分：1
