登录
首页 » Verilog » FPGA NIOS II W5500

FPGA NIOS II W5500

于 2022-08-10 发布 文件大小:4.01 MB
0 112
下载积分: 2 下载次数: 1

代码说明:

Altera FPGA  NIOS II 通过W5500芯片完成网络TCP/IP通讯。

下载说明:请别用迅雷下载,失败请重下,重下不扣分!

发表评论

0 个回复

  • VGA的verilog实现
    VGA的verilog实现,通过宏控制输出格式,兼容altera的avalon总线。
    2022-09-15 09:55:02下载
    积分:1
  • xilinx-FPGA
    xilinx FPGA技术详解,从设计流程到设计注意点(xilinx FPGA technology Detailed Design points, from the design process to)
    2012-08-10 13:07:41下载
    积分:1
  • SD卡控制器verilog
    说明:  sd卡读写,仿真模型,testbanch测试文件(sdcard read write and sdcard model)
    2021-04-21 16:28:49下载
    积分:1
  • vhdl
    vhdl状态机设计,文件简单详细易懂,可以使用在交通灯,文件配置等系统上。(vhdl state machine design, simple, detailed and easy to understand, you can use the traffic light system file configuration file.)
    2012-09-04 15:21:53下载
    积分:1
  • 基于Avalon总线的PWM的实现,verlog语言编程
    资源描述基于Avalon总线的PWM的实现,verlog语言编程
    2022-09-14 06:40:03下载
    积分:1
  • Verilog HDL 频率可调的任意波形发生器
    Verilog HDL数字系统设计项目,频率可调的任意波形发生器,可以输出正弦波、方波、三角波和反三角四种波形(Verilog HDL digital system design projects, adjustable frequency arbitrary waveform generator can output sine wave, square wave, triangle wave and the anti-triangular four waveform)
    2011-05-08 03:21:34下载
    积分:1
  • dr6—ise-F
    用FPGA开发板的按键作为电子表的时间初值设置控制信号,数码管当前时间值输出。用按键选择分别输出:分、秒、1/10秒。(With FPGA development board button, as the time value of the electronic table, set the control signal, digital tube current time value output. Select output by buttons: minutes, seconds, and 1/10 seconds.)
    2017-10-11 21:19:55下载
    积分:1
  • ds190-Zynq-7000-Overview
    zedboard的资料说明书,可以帮助你理解(zedboard data sheets, can help you understand)
    2012-11-06 10:51:14下载
    积分:1
  • gtwizard_254_127_ex_1113_3
    配置GTH ip的例子工程,选用7 series 芯片的GTH 113quad的四个通道,在程序中每个链路利用自己的恢复时钟进行数据解码,所以四个通道可以各自独立运行;成功工作在2.54Gb/s的链路状态,长时间(>24小时)的测试,误码率一直为0.(The GTH ip example project is configured with four channels of the GTH 113quad of the 7 series chip. Each link in the program uses its own recovery clock for data decoding, so the four channels can operate independently; the successful operation is at 2.54Gb/ The link state of s, long time (>24 hours) test, the bit error rate has been 0.)
    2019-06-17 21:33:56下载
    积分:1
  • LCD1602-TEST
    利用verilog驱动LCD1602 本实验是用LCD1602显示英文。(LCD带字库)(//Use verilog driver LCD1602// video tutorial for all of us 21EDA e-learning board// The experiment is LCD1602 display in English. (LCD with font))
    2013-12-16 13:51:35下载
    积分:1
  • 696516资源总数
  • 106442会员总数
  • 11今日下载