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sram_sp_hse_8kx8
SRAM 8K*8 芯片存储器 芯片存储器 芯片存储器(SRAM 8K*8
Chip memory
Chip memory)
- 2018-08-26 18:50:04下载
- 积分：1
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bt656_decode
将嵌入式BT656格式数据解码出带行场同步信号的YCbCr422格式数据(Decoding Embedded BT656 Format Data to YCbCr422 Format Data with Field Synchronization Signa)
- 2021-01-28 10:38:35下载
- 积分：1
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ep2c5核心电路SCH
EP2C5核心电路原理图，包括protel文件及其相应封装库-EP2C5 Core circuit Sch
- 2023-02-03 21:30:03下载
- 积分：1
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STM32F103ZEt6_NORFlash
1、FSMC全称是静态存储控制器，用来高速操作外部SRAM，NOR，NAND等，广泛用来驱动LCD
MCU的FSMC配置在fsmc_nor.c，你也可以查阅相关资料。
2、此例程通过读写外部M29W128，熟悉FSMC的配置以及操作。(1, FSMC stands for static memory controller for high-speed operation of external SRAM, NOR, NAND, widely used to drive the LCD MCU FSMC configuration in fsmc_nor.c, you can also access to relevant information. This routine by reading and writing external M29W128 familiar with the configuration and the operation of the FSMC.)
- 2012-11-26 11:08:20下载
- 积分：1
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verilog-ethernet
说明： Collection of Ethernet-related components for gigabit, 10G, and 25G packet processing (8 bit and 64 bit datapaths). Includes modules for handling Ethernet frames as well as IP, UDP, and ARP and the components for constructing a complete UDP/IP stack. Includes MAC modules for gigabit and 10G/25G, a 10G/25G PCS/PMA PHY module, and a 10G/25G combination MAC/PCS/PMA module. Includes various PTP related components for implementing systems that require precise time synchronization. Also includes full MyHDL testbench with intelligent bus cosimulation endpoints.
- 2021-04-17 23:38:52下载
- 积分：1
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测试VANET应用程序
他延误用户inrandom经历过或基于竞争的MAC方案是无界;用户可能需要等待论坛很长一段时间，直到他/她发送一些数据的机会。在otherhand，通过根据一定的deterministicpattern，这被称为由梅西和马特仕协议序列调度所述数据分组，延迟的hardguarantee可以完成。
- 2022-07-10 10:09:43下载
- 积分：1
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坦克游戏的VHDL代码
坦克游戏用VHDL语言编写。Altera的随身携带套件DE1。PS2键盘接口和VGA
- 2022-03-14 20:16:04下载
- 积分：1
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svpwm3
说明： 基於空間向量調變的開關法，在於載波做比較切出方波再送至開關讓馬達啟動(Based on the switching method of space vector modulation, the square wave is cut out for carrier comparison and sent to the switch to start the moto)
- 2019-01-04 16:07:37下载
- 积分：1
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exercise3
用verilog实现dsp与Fpga接口的同步设计，其功能包括读写操作及四个功能模块，采用两个fifo实现不同时钟域的地址与数据的转换，在quartus ii11.0环境下运行，运行此程序之前需运行将调用fifo。(Dsp using verilog achieve synchronization with Fpga interface design, its features include read and write operations and four functional modules, using two different clock domains to achieve fifo address and data conversion in quartus ii11.0 environment to run, run this program required before running calls fifo.)
- 2013-08-30 11:12:09下载
- 积分：1
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JIAOTONGDENG
用VERILOG实现 交通灯控制，且运行正确，希望有帮助(Use VERILOG implementation traffic light control, and operation right, hope to have help)
- 2014-01-05 20:38:03下载
- 积分：1
