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OVM(Open Verification Methdology) for system verilog or systemC

于 2022-08-12 发布文件大小:2.89 MB

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OVM(Open Verification Methdology) for system verilog or systemC

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主要介绍了等精度频率测量原理，该原理具有在整个测试频段内保持高精度频率测量的优点同时在该原理基础上，采用了Verilog HDL语言设计了高速的等精度测频模块，并且利用EDA开发平台QUARTUS11 3 .0对CPLD芯片进行写人，实现了计数等主要逻辑功能还使用C语言设计了该等精度频率计的主控程序以提高测量精度。本设计实现了对频率变化范围较大的信号进行频率测量，能够满足高速度、高精度的测频要求。-Introduced, such as the accuracy of frequency measurement principle, the principle has in the entire test frequency to maintain the advantages of high precision frequency measurement at the same time the basis of the principle of using the Verilog HDL language, such as the design of a high-speed precision frequency measurement module, and use of EDA Development platform QUARTUS11 3 .0 on CPLD chip to write, and achieved a count of the main logic function, such as the use of C language is also designed such precision the frequency of control procedures to enhance measurement accuracy. This design achieved a wide range of frequency changes in signal frequency measurement, to meet the high-speed, high precision frequency measurement requirements.

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OVM(Open Verification Methdology) for system verilog or systemC

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