登录
首页 » VHDL » Verilog based on the eight

Verilog based on the eight

于 2022-08-13 发布 文件大小:120.37 kB
0 124
下载积分: 2 下载次数: 1

代码说明:

基于Verilog的八层电梯设计,能够实现自动化的电梯控制。-Verilog based on the eight-lift designed to automate the elevator control.

下载说明:请别用迅雷下载,失败请重下,重下不扣分!

发表评论

0 个回复

  • 卡内基梅陇大学verilog课程讲义-unlocked
    说明:  verilog讲义 卡内基梅陇大学verilog课程讲义-unlocked 卡内基梅陇大学verilog课程讲义-unlocked(Verilog Course Lectures at Carnegie Mellon, University Verilog Course Lectures at Carnegie Mellon University Verilog Course Lectures at Carnegie Mellon University)
    2020-06-20 18:00:02下载
    积分:1
  • VHDL语言写的频率计的程序,内带完整的技术报告
    VHDL语言写的频率计的程序,内带完整的技术报告-VHDL write the frequency of procedures, brought integrity of the technical report
    2022-02-20 00:46:02下载
    积分:1
  • 最近组长给分配的任务,这几天一直在做,比较郁闷的是用的器件是XC400XL系列的,只有ISE4.1支持,用惯了7.1i的我还是要适应一阵子(关键4.1是一个试用...
    最近组长给分配的任务,这几天一直在做,比较郁闷的是用的器件是XC400XL系列的,只有ISE4.1支持,用惯了7.1i的我还是要适应一阵子(关键4.1是一个试用版的)。挺折腾的,不说了,放上顶层模块:-。。。
    2022-04-28 08:18:32下载
    积分:1
  • walkthrough1
    switching the lights debouncing , toggle
    2010-02-10 03:07:08下载
    积分:1
  • sample_SPI
    这是一个瑞萨R78/G13的SPI演示程序,详细的放置了说明,很有用的源码(This is one of the SPI Renesas R78/G13 demonstration program, placed a detailed description of very useful source)
    2013-09-03 02:59:19下载
    积分:1
  • pipeline_booth_mult_16
    用流水线的方法实现16位乘法器,运算速度快,消耗时钟资源少(Pipeline method to realize 16-bit multiplier, which is fast in operation and consumes less clock resources)
    2020-09-29 18:17:44下载
    积分:1
  • CAN协议控制器的Verilog实现
    说明:  基于FPGA的CAN总线控制器,VERILOGHDL源代码,Q2仿真实现。可用。(FPGA-based CAN Bus Controller, VERILOGHDL source code, Q2 Simulation. Available.)
    2020-11-26 15:29:31下载
    积分:1
  • 中值滤波算法
    中值滤波实现。选择在Vivado软件上采用Verilog语言来编写中值滤波算法,搭建出完整的数据处理系统架构,通过仿真和验证来判断数据的处理效果,并在实际的设计过程中根据出现的问题提出解决方案。(Median filter implementation. The author chose Verilog language to write the median filter algorithm in Vivado software, built a complete data processing system architecture, judged the data processing effect through simulation and verification, and proposed a solution according to the problems in the actual design process.)
    2018-05-30 13:44:03下载
    积分:1
  • subway-ticket-vending-system
    本设计是基于FPGA设计一个地铁自动售票系统。 本设计采用自顶向下的模块化设计方法,基于FPGA使用VHDL语言设计制作一个地铁自动售票控制系统,该系统能出售2条线路3种不同价位的票,完成售票、找零、显示等功能。(The design is based FPGA design of a subway ticket vending system. This design uses a top-down, modular design method, a subway ticket vending control system based on FPGA using VHDL language design, the system can sell two lines of different priced tickets, complete the ticket, give change, display and other functions .)
    2013-02-27 12:59:49下载
    积分:1
  • airthmatic & logic unit
    airthmatic & logic unit
    2023-02-23 08:10:03下载
    积分:1
  • 696518资源总数
  • 106164会员总数
  • 18今日下载