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breath
利用verilog写的PWM 程序,来实现产生呼吸灯的效果。(Using xerilog to generate breathing lamp)
- 2020-06-17 04:40:01下载
- 积分:1
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McBSP
CPLD对mcbsp的收发操作,占用资源很少(CPLD to mcbsp transceiver operation, small footprint)
- 2011-09-14 16:19:51下载
- 积分:1
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keyscan
利用VHDL语言编写的4*4键盘扫描程序,经过测试,可以放心使用。(Using VHDL language 4* 4 keyboard scanning procedures, tested, safe to use.)
- 2013-09-28 21:48:45下载
- 积分:1
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FFT
FFT with FIR created by students in univercity
- 2015-06-22 14:57:30下载
- 积分:1
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MAC
在FPGA硬件上,使用verilog语言编写的一个乘累加器程序。(FPGA hardware, a multiply accumulator verilog language program.)
- 2012-10-18 20:28:25下载
- 积分:1
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DCM_SP
数字时钟管理器,xilinx公司开发板集成时钟,实现分频、倍频等功能。(Digital clock managers, xilinx development board integrated clock divider, multiplier, and other functions.)
- 2021-02-19 09:59:44下载
- 积分:1
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RS(204-188)decoder_verilog
采用verilog实现的有限域GF(28)弱对偶基乘法器,本原多项式: p(x) = x^8 + x^4 + x^3 + x^2 + 1 ,多项式基: {1, a^1, a^2, a^3, a^4, a^5, a^6, a^7},弱对偶基: {1+a^2, a^1, 1, a^7, a^6, a^5, a^4, a^3+a^7}(Verilog achieved using the finite field GF (28) weak dual basis multiplier)
- 2016-06-12 16:31:51下载
- 积分:1
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16位CUPIP核,完全运行的好的东西,可以直接拿来用的!
16位CUPIP核,完全运行的好的东西,可以直接拿来用的!-16 CUPIP nuclear, full of good things to run, can be directly used to use!
- 2022-07-27 19:00:19下载
- 积分:1
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PWM
用Verilog实现的脉冲宽度调制程序,在quartus平台上测试成功。(Using Verilog implementation of pulse width modulation, in quartus platform test successfully.)
- 2017-08-09 16:46:13下载
- 积分:1
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BCD-counter
一个2位的BCD码十进制加法计数器电路,输入为时钟信号CLK,进位
输入信号CIN,每个BCD码十进制加法计数器的输出信号为D、C、B、A和进位输出信号COUT,输入时钟信号CLK用固定时钟,进位输入信号CIN.
(A 2-bit BCD code decimal adder counter circuit input as the clock signal CLK, a carry input signal CIN, D, C, B, A, and the carry output signal COUT, each BCD code decimal adder counter' s output signal, the input clock signal CLK Fixed clock, binary input signal CIN.)
- 2020-10-28 19:29:58下载
- 积分:1