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spring 入门教程 是繁体版的 不过书籍质量不错对spring一些概念性的东西讲的满好的...
spring 入门教程 是繁体版的 不过书籍质量不错对spring一些概念性的东西讲的满好的
- 2022-02-04 00:16:51下载
- 积分：1
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支持向量机的中的一个功能的改进，对于识别方法有所提高
支持向量机的中的一个功能的改进，对于识别方法有所提高-Support vector machines in a functional improvement, for improved identification methods
- 2022-03-21 18:46:58下载
- 积分：1
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用于ansys的二次开发,很好用,确实值得收场
用于ansys的二次开发,很好用,确实值得收场- be the devlopment of ansys for the second time
- 2022-01-21 19:34:51下载
- 积分：1
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alsdkag spkdfg
关于开发驱动的代码】
关于开发驱动的代码】
关于开发驱动的代码】
关于开发驱动的代码】
-alsdkag spkdfg
- 2023-03-10 06:20:03下载
- 积分：1
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非常好的外文IDL开发教材，深入浅出的介绍了用如何IDL开发程序，包含详细的实例演示。...
非常好的外文IDL开发教材，深入浅出的介绍了用如何IDL开发程序，包含详细的实例演示。-a very good foreign language teaching materials about IDL Developed , describes in simple terms how to use IDL development process, with detailed examples of presentation.
- 2022-01-30 16:30:53下载
- 积分：1
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IEEE 802.11f
IEEE 802.11F-2003 IEEE Recommended Practice for Multi-Vendor Access Point Interoperability via an Inter-Access Point Protocol Across Distribution Systems Supporting IEEE 802.11 Operation -IEEE 802.11F-2003 IEEE Recommended Practice for Multi-Vendor Access Point Interoperability via an Inter-Access Point Protocol Across Distribution Systems Supporting IEEE 802.11 Operation
- 2022-08-20 03:41:54下载
- 积分：1
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Struts2・0API参考手册开发指南
Struts2・0API参考手册开发指南
- 2023-05-14 15:00:10下载
- 积分：1
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FPGA pipelined designs on paper This work investigates the use of very deep pipe...
关于FPGA流水线设计的论文
This work investigates the use of very deep pipelines for
implementing circuits in FPGAs, where each pipeline
stage is limited to a single FPGA logic element (LE). The
architecture and VHDL design of a parameterized integer
array multiplier is presented and also an IEEE 754
compliant 32-bit floating-point multiplier. We show how to
write VHDL cells that implement such approach, and how
the array multiplier architecture was adapted. Synthesis
and simulation were performed for Altera Apex20KE
devices, although the VHDL code should be portable to
other devices. For this family, a 16 bit integer multiplier
achieves a frequency of 266MHz, while the floating point
unit reaches 235MHz, performing 235 MFLOPS in an
FPGA. Additional cells are inserted to synchronize data,
what imposes significant area penalties. This and other
considerations to apply the technique in real designs are
also addressed.-FPGA pipelined designs on paper This work invest
- 2022-11-28 12:05:03下载
- 积分：1
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一个不同的人软件工程的书籍，“一个软件开发。
一个不同于人月软件工程书籍的 “一本关于软件开发的有效技术书籍” 中文名字是《代码大全》 （中文pdf版本）-a different person software engineering books, "a software development on the effective technical books," the Chinese name of "code Encyclopaedia" (Chinese version pdf)
- 2022-07-21 20:31:08下载
- 积分：1
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java比较经典的一本书，希望对大家有用哦
java比较经典的一本书，希望对大家有用哦-java comparison of a classic book, we hope to useful oh
- 2022-01-22 07:39:27下载
- 积分：1
