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FPGA设计的I2C总线控制器的MASTER端的程序
FPGA设计的I2C总线控制器的MASTER端的程序-FPGA Design of I2C Bus Controller MASTER-side procedures
- 2022-03-14 08:16:35下载
- 积分：1
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i2s_input
基于FPGA的i2s接口输入模块设计，其中有原理图和verilog源码，可在Quartus环境下进行仿真(FPGA-based i2s interface input module design, including schematics and verilog source code, can be simulated in Quartus environment)
- 2020-12-14 16:49:14下载
- 积分：1
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16位浮点FFT算法的VHDL实现有测试文件！
16位浮点FFT算法的VHDL实现有测试文件！-16-bit floating-point FFT algorithm VHDL realization of a test file!
- 2022-01-28 18:16:34下载
- 积分：1
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VHDL实现SPI功能源代码
VHDL实现SPI功能源代码
-- The SPI bus is a 3 wire bus that in effect links a serial shift
-- register between the "master" and the "slave". Typically both the
-- master and slave have an 8 bit shift register so the combined
-- register is 16 bits. When an SPI transfer takes place, the master and
-- slave shift their shift registers 8 bits and thus exchange their 8
-- bit register values.-SPI realize the functional VHDL source code The SPI bus is a 3 wire bus that in effect links a serial shift register between the
- 2022-01-26 00:50:40下载
- 积分：1
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多功能卡的源代码，verilog编写，用于多功能的数据接收
多功能卡的源代码，verilog编写，用于多功能的数据接收-verilog code of mutiple function card
- 2022-09-30 12:00:08下载
- 积分：1
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src
yuv444 与yuv422相互转换verilog语言(yuv444 to yuv422)
- 2021-01-20 14:38:41下载
- 积分：1
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YCbCr444_YCbCr422
FPGA YCbCr444转YCbCr422实验 很好的参考(FPGA EP4CE40F23C6 YCbCr444 turn YCbCr422 experiment)
- 2021-01-25 10:08:38下载
- 积分：1
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代码基于VHDL语言的个文化代码有用的但是可能有错误下在是倾销心...
代码基于VHDL语言的个文化代码有用的但是可能有错误下在是倾销心-VHDL code based on the cultural code useful but may be under the wrong heart is dumping
- 2022-04-13 03:11:13下载
- 积分：1
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ABencode
FPGA实现增量式光栅尺正交脉冲解码，基于Verilog(FPGA realization of incremental grating ruler orthogonal pulse decoding, based on Verilog)
- 2020-11-21 20:59:36下载
- 积分：1
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bhas
this is a vhdl program...
- 2013-08-17 23:30:56下载
- 积分：1
