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UART_FPGA
此vhdl程序实现了在FPGA上构建UART通信串口。分为两部分，UART的发送端transfer和接收端receiver。需要外部根据需求提供波特率时钟。(This program implements the building vhdl UART serial interface on the FPGA. Divided into two parts, UART transfer sender and receiver receiver. Required to provide the baud clock external demand.)
- 2015-03-04 11:02:17下载
- 积分：1
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Quartus flv configuration and commissioning of the
QUARTUS 的配置及调试
flv的
-Quartus flv configuration and commissioning of the
- 2023-08-05 13:40:04下载
- 积分：1
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用VHDL编写简单的直流电机控制方法.供大家参考.
用VHDL编写简单的直流电机控制方法.供大家参考.-use VHDL to prepare a simple DC motor control methods. For your reference.
- 2022-07-09 16:31:01下载
- 积分：1
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在quartus中使用IP核的实际例子与流程
在quartus中使用IP核的实际例子与流程-The use of IP in the Quartus practical examples and nuclear flow
- 2022-08-07 01:33:34下载
- 积分：1
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这是个UART发送的VHDL程序，调试过，还可以
这是个UART发送的VHDL程序，调试过，还可以-This is a UART to send the VHDL program, debug, and can also be
- 2022-08-10 15:14:18下载
- 积分：1
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EEPROM
控制器灯具有线和无线控制器采用STC11F02做的(Controller for lamp wired and wireless controller using STC11F02 to do)
- 2012-01-05 14:45:10下载
- 积分：1
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rtl_DRAM
本程式為使用Verilog語言寫控制DRAM的控制模塊, 可以簡易的控制DRAM IC, 本程式已經過系統驗證.(program for the use of the Verilog language to write the control of DRAM control module, be easy to control DRAM IC, the program has been systematically verified.)
- 2006-12-05 11:31:42下载
- 积分：1
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deng
HDL verilog 电子密码锁 输入错误后有报警 输入正确后有提示(HDL Verilog electronic code lock input errors have prompted alarm input is correct)
- 2012-06-27 19:25:53下载
- 积分：1
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fpga0023202323
FPGA时序分析说明。对于高速时钟设计中的时序分析与约束有帮助(FPGA,TIME)
- 2010-11-01 15:49:34下载
- 积分：1
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通过实例的VHDL程序设计
VHDL programming by example
- 2022-03-19 05:46:52下载
- 积分：1
