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rs-codec(255-223)
RS编码是一种纠错码，本程序实现RS（255，223）用FPGA 实现RS编码，程序在Quartus II中调试通过。(RS coding is an error-correcting codes, the procedures for the realization of RS (255,223) with FPGA realization of RS codes, in the Quartus II program through the debugger.)
- 2021-05-13 00:30:02下载
- 积分：1
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With VHDL Design and Implementation of the multi
用vhdl设计实现的多功能电子钟，可有日历，闹钟，修改等多种功能-With VHDL Design and Implementation of the multi-functional electronic bell, can have a calendar, alarm clock, to amend a variety of functions such as
- 2022-03-11 03:55:41下载
- 积分：1
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progconterful
four bit counter verlog source code for veriwell including test bench
- 2010-03-29 18:54:45下载
- 积分：1
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bingchuan
说明： 简单的vhdl的四位并串转换程序，可以实现数据的并串转换(Simple vhdl string of four and the conversion process, can convert the data and the string)
- 2011-04-02 12:16:35下载
- 积分：1
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vb3draw
这是一个讲究的的 介绍VB在犀牛软件里的 很好的东西 你会满意的 相信我(you will be glad)
- 2013-11-28 14:32:37下载
- 积分：1
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FDPIM_Encode
关于语音通信信道调制的程序代码，是论文的仿真程序(About voice communication channel modulation code, the authors of the paper simulation program)
- 2013-12-11 09:27:39下载
- 积分：1
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fft
说明： 用FPGA实现8点fft，整个代码使用verilog编写，主要运用了加法器和乘法器，简单易懂(8-point FFT with FPGA, The whole code is written by Verilog, mainly using adder and multiplier, which is easy to understand)
- 2021-03-29 20:59:10下载
- 积分：1
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一个用FPGA语言设计数字秒表的程序，有相关的源程序和说明
一个用FPGA语言设计数字秒表的程序，有相关的源程序和说明-FPGA design using a digital stopwatch language of the procedures and instructions related to the source
- 2022-02-02 02:15:47下载
- 积分：1
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关于寄存器重命名register reallocation,VHDL
关于寄存器重命名register reallocation,VHDL-Register on rename register reallocation, VHDL
- 2022-02-09 20:31:31下载
- 积分：1
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１３键键盘的ＶＨＤＬ顶层文件，我是初学着，希望对初学者有用...
１３键键盘的ＶＨＤＬ顶层文件，我是初学着，希望对初学者有用-13 key keyboard VHDL top-level document, I was a novice with the hope that useful for beginners
- 2022-03-04 05:06:34下载
- 积分：1
