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BaseLine1
this is an peak detection alguritm,in this matlab code u can clean base line noise to have clear ECG signal
- 2012-12-12 00:58:21下载
- 积分：1
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实现了简单的电子表功能，是24小时，用VHDL所编写的，quartus ii 7.2...
实现了简单的电子表功能，是24小时，用VHDL所编写的，quartus ii 7.2-To achieve a simple spreadsheet functions, is 24 hours, using VHDL prepared, quartus ii 7.2
- 2023-05-19 01:30:03下载
- 积分：1
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Altera 基础篇公司书籍源码
Altera 基础篇公司书籍源码-Altera Corporation based on chapter books-source
- 2022-10-29 10:20:03下载
- 积分：1
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clk_div3
在fpga中对于pll无法完成的分频，可采用计数方式，本例用状态机实现对时钟的奇数分频。(Pll in fpga can not be completed in the sub-frequency counting method can be used, in this case with the state machine to achieve an odd number on the clock frequency.)
- 2010-07-28 20:03:41下载
- 积分：1
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11 阶FIR 数字滤波器,verolog描述，通过modelsim 6.0 仿真，Quartue综合...
11 阶FIR 数字滤波器,verolog描述，通过modelsim 6.0 仿真，Quartue综合-11-order FIR digital filter, verolog description, modelsim 6.0 through simulation, Quartue integrated
- 2022-10-31 17:45:02下载
- 积分：1
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MSK
FPGA中实现的MSK调制，带modelsim仿真。实际系统测试通过：载波和调制波信号频率可调。调制框图请参见樊昌信 通信原理247页(MSK modulation implemented in FPGA with modelsim simulation. The actual test system: a carrier wave signal and the modulation frequency is adjustable. See Fan Changxin modulation block diagram of communication theory 247)
- 2021-05-13 08:30:02下载
- 积分：1
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clk_generator
时钟分频代码，PWM产生 RTL 源代码。(clock divider，PWM generator RTL Source Code)
- 2013-08-18 09:29:42下载
- 积分：1
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33
说明： 高速宽带数字调制技术的研究，该论文也是非常经典的，希望对大家有帮助(High-speed broadband digital modulation technology, the paper is also very classic, I hope all of you help)
- 2009-07-03 11:47:02下载
- 积分：1
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sch_tbf
Token Bucket Filter queue.
- 2013-05-06 11:34:24下载
- 积分：1
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add_verilog
2位全加器，实现全加器的功能，有近位的加法，输出也有近位，还有testbench,进行验证，验证通过(Two full adders, to achieve full adder function, nearly bit adder, there are nearly bit output)
- 2014-05-14 18:56:33下载
- 积分：1
