-
异步FIFO代码
异步fifo设计代码,包含完整过程,需要的朋友可以参考,实际设计代码,参考了多个版本,通过了项目验证,已经实际应用。
- 2022-02-24 12:15:30下载
- 积分:1
-
FPGA DDS
使用DE2实现DDS,步骤简单,配置管脚可自查看(Using DE2 to realize DDS, the steps are simple and the pins can be self-checked.)
- 2020-06-23 10:00:01下载
- 积分:1
-
using_memory_allocation_mger
vmm primer的使用使用文档,和之前vmm primer源代码配套使用!(vmm the primer use of the use of the document, and before supporting vmm the primer the source code to use!)
- 2012-12-23 22:43:30下载
- 积分:1
-
Xilinx-Timing
Xilinx FPGA 时序约束资料,原厂出品,经典不需要理由(Xilinx FPGA timing constraint information, original, classic no reason)
- 2013-05-17 09:31:26下载
- 积分:1
-
grlib-gpl-1.1.0-b4108
gaisler公司在2011年发布的的leon3的源代码!(source code of leon3 )
- 2012-05-12 00:12:20下载
- 积分:1
-
aurora_IP
Aurora协议是一款高带宽、低成本、可扩展、框架简洁、适合点对点串行数据传输的协议。(Aurora protocol is a high-bandwidth, low-cost, scalable, simple framework for point to point serial data transfer protocol.)
- 2017-03-10 17:16:22下载
- 积分:1
-
digital_clock
数字钟通过verilog实现,并且支持Modelsim仿真,通过实验验证(The digital clock is implemented by Verilog and supports Modelsim simulation)
- 2020-06-18 05:00:02下载
- 积分:1
-
banjian
完成一个1位全减器的设计。以全减器为元件程序完成8位减法器设计。(Completed a one minus the whole design. Full reduction is to complete eight subtraction element program design.)
- 2015-06-26 21:17:49下载
- 积分:1
-
float_multi
说明: FPGA Verilog浮点数乘法运算,采用单精度浮点型小数格式,运算结果精度可设置,可封装成IP核(FPGA Verilog floating-point multi operation, using single precision floating-point decimal format, the accuracy of the operation results can be set, can be packaged into IP core)
- 2020-07-02 01:20:01下载
- 积分:1
-
UML_2_Pour_les_bases_de_donnees
UML2 apprendre a modeliser a l aide de UML
- 2014-02-25 01:32:23下载
- 积分:1