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Receiver
该程序是整个OFDM接收机的程序，希望对做这方面的朋友用些帮助，也希望朋友们和我一起探讨OFDM收发信机。(The program is the whole OFDM receiver process, hope to do in this area with some friends to help and also hope that friends and I explore OFDM transceiver.)
- 2010-01-03 13:44:38下载
- 积分：1
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MIPSTOP
说明： misp顶层文件，verilog实现misp架构，并且支持modelsim仿真(Verilog implements MISP architecture and supports Modelsim simulation)
- 2020-06-18 04:40:02下载
- 积分：1
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uart16550 ip core UART VHDL source code
uart16550 ip core 通用异步收发器vhdl源代码-uart16550 ip core UART VHDL source code
- 2022-07-11 01:23:07下载
- 积分：1
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regress-900055
The Date prototype object is itself a Date object (its [[Class]] is "Date") whose value is NaN.
- 2013-12-27 00:29:58下载
- 积分：1
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基于VHDL的I2C程序0003,很不错的论文及程序，，大家快下啊
基于VHDL的I2C程序0003,很不错的论文及程序，，大家快下啊-based on the I2C procedures VHDL 0003, a very good paper and procedures, we quickly under ah
- 2022-03-21 08:29:16下载
- 积分：1
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matrix_class
it is a matrix library. it is needed for fir fier.
- 2014-08-29 22:29:24下载
- 积分：1
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ALU用VHDL项目
ALU using VHDL project
- 2022-03-22 23:35:27下载
- 积分：1
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is done in the laboratory in the loss of 60 counts, and LED show.
是我们在在实验室做的摸60计数，并用LED显示出来。-is done in the laboratory in the loss of 60 counts, and LED show.
- 2022-03-21 19:17:50下载
- 积分：1
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clock_smg
自己做的数码管显示的时钟 一个非常简单的FPGA时钟 用累加做的(To do their own digital display clock of the FPGA clock is a very simple to do with the cumulative)
- 2011-09-27 21:07:54下载
- 积分：1
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乘法器是硬件设计中的很常见也很重要的一个模块，它的VHDL硬件实现很好的解决了软件编程中做乘法速度慢的问题，在实时高速系统应用中或DSP软核或数字信号处理硬件实...
乘法器是硬件设计中的很常见也很重要的一个模块，它的VHDL硬件实现很好的解决了软件编程中做乘法速度慢的问题，在实时高速系统应用中或DSP软核或数字信号处理硬件实现算法中，经常能使用到乘法器，所以经典的高速乘法器IP 很有参考价值-Multiplier is a common and important module in hardware designing.Its VHDL addresses the low speed of multiplication in software programming. Multiplier is often used in real-time high-speed system application , DSP soft core or hardware implementation of digital signal processing,so it is worthful to know classic high-speed multiplier IP
- 2022-03-03 00:48:52下载
- 积分：1
