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ABS_17_BIT_SOURCE_CODE
说明： 多摩川绝对值编码器的NRG协议源代码,我们公司用的，我修改的解码程序(Tamagawa NRG absolute encoder protocol source code, used by our company, I modified decoding process)
- 2009-07-30 21:06:58下载
- 积分：1
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pinlvji
频率计
测量范围1-100MHz
测量阈值0.1s
计数部分为FPGA/CPLD
语言VHDL
显示部分为51
单片机加八位数码管
语言C(Frequency meter
Measuring range 1-100 MHZ
Measure threshold is 0.1 s
Count part of FPGA/CPLD
Language VHDL
Display part of 51
MCU with eight digital tube
Language C)
- 2020-10-30 20:39:55下载
- 积分：1
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4：2优先编码器的VHDL代码
4：2优先编码设计中的VHDL来为每个输入分配优先级。在CMOS布局1复用器：还设计了4个
- 2022-02-11 13:12:33下载
- 积分：1
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Great guide for writing VHDL
Great guide for writing VHDL
- 2023-05-21 15:20:03下载
- 积分：1
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verilog_DATA_displays
使用verilog语言，滚动显示“verilog”字符串程序代码及相关说明(Using verilog language, scrolling display " verilog" string code and instructions)
- 2014-01-16 10:49:55下载
- 积分：1
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frequency-agility
本程序为捷变频信号的verilog源代码设计实现的仿真，并含有相应捷变频信号在MATLAB仿真的结果(The procedure for the Czech Republic converted signal verilog source code design and implementation of the simulation, and the Czech Republic frequency signal containing the corresponding simulation results in MATLAB)
- 2015-10-15 10:37:54下载
- 积分：1
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基于VHDL的电梯系统
应用背景基于VHDL实现四层电梯的运动，实现电梯的正常运转关键技术VHDL，状态机，编译码器，触发器，比较器。
- 2023-02-04 04:40:04下载
- 积分：1
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用FPGA实现CRC算法，只用一个脉冲就能实现，比传统的移位算法大大节约时间...
用FPGA实现CRC算法，只用一个脉冲就能实现，比传统的移位算法大大节约时间-Using FPGA to achieve CRC algorithm, only one pulse will be able to realize, than the traditional algorithm greatly saving time shift
- 2022-07-14 15:39:31下载
- 积分：1
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infrared_receive
红外接收处理，根据外部波形记录波形的高低电平时间，从而得到波形数据。(Infrared receiver processing, according to the external waveform waveform record high and low times, resulting waveform data.)
- 2013-09-27 11:09:02下载
- 积分：1
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UART_FPGA
此vhdl程序实现了在FPGA上构建UART通信串口。分为两部分，UART的发送端transfer和接收端receiver。需要外部根据需求提供波特率时钟。(This program implements the building vhdl UART serial interface on the FPGA. Divided into two parts, UART transfer sender and receiver receiver. Required to provide the baud clock external demand.)
- 2015-03-04 11:02:17下载
- 积分：1
