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用vhdl实现24小时计数器，方法简单实用。 仿真环境MAXPLUS
用vhdl实现24小时计数器，方法简单实用。 仿真环境MAXPLUS--use VHDL to achieve 24-hour counter, simple and practical method. Simulation environment Segments-
- 2022-03-24 12:46:20下载
- 积分：1
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doorlock
基于FPGA设计的电子密码锁是一个小型的数字系统，与普通机械锁相比，具有许多独特的优点：保密性好，防盗性强，可以不用钥匙，记住密码即可开锁等。(FPGA-based design of the electronic code lock is a small digital system. It has many unique advantages：good privacy and security , it do not need the key but remember password to unlock, and so on while it compare to ordinary mechanical locks.)
- 2013-12-25 21:24:41下载
- 积分：1
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rscode
RS编码器在fpga上的实现，用的modelsim开发环境(RS encoder in the realization of the fpga, development environment used in modelsim)
- 2009-06-11 21:45:49下载
- 积分：1
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kalman_mppt-master
filter kalman mppt for PV
- 2020-10-04 13:27:39下载
- 积分：1
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vga
利用FPGA控制VGA显示器显示字符汉字的程序，里面有注释。(VGA display with FPGA control procedures Kanji characters, there are comments.)
- 2013-11-25 11:59:13下载
- 积分：1
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ug835-vivado-tcl-commands
说明： Vivado是Xilinx最新的FPGA设计工具，支持7系列以后的FPGA及Zynq 7000的开发。与之前的ISE设计套件相比，Vivado可以说是全新设计的。无论从界面、设置、算法，还是从对使用者思路的要求，都是全新的。看在Vivado上，Tcl已经成为唯一支持的脚本，此文件是vivado是tcl命令的集合。(Vivado is Xilinx's latest FPGA design tool that supports development of FPGAs and Zynq 7000s in the 7 series and beyond. Compared with the previous ISE design suite, Vivado can be said that the new design. No matter from the interface, settings, algorithms, or from the user ideas, are new. Look at Vivado, Tcl has become the only supported script, this file is vivado tcl command collection.)
- 2020-10-26 22:50:00下载
- 积分：1
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bcd
it shows bcd counter
- 2013-01-01 16:16:48下载
- 积分：1
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uart
uart 发送模块接收模块及tb，其中可以选择不同波特率进行收发，代码带有详细注释。(UART sending module and receiving module)
- 2020-06-20 20:00:02下载
- 积分：1
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lbs_fpga_upld
利用FPGA实现与powerpc的localbus数据接口代码。用verilog实现(localbus interface with PowerPC using Verilog)
- 2020-11-25 22:59:38下载
- 积分：1
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sdcard_mass_storage_controller
A host controlled ot control sd cards
- 2021-04-29 13:58:43下载
- 积分：1
