-
circuit_timing
verilog延时电路的不同写法，和综合能否。可对比学习(Different wording verilog delay circuit, and comprehensive ability. Comparable learning)
- 2014-05-14 18:02:44下载
- 积分：1
-
LS-versus-MMSE
这是基于MIMO-OFDM的同步算法研究的源程序。本程序采用的极大似然估计的方法。(This is based on MIMO-OFDM synchronization algorithm source code. The program uses the method of maximum likelihood estimates.
)
- 2012-12-13 15:32:49下载
- 积分：1
-
gundong
说明： 通过按键输入学号，并循环显示：
电路功能描述：通过Ego1上的按键输入自己的学号（8位10进制数），并存储在32位的寄存器中；8位10进制数输入完成后，实现滚动显示效果。(Enter the student number by pressing the key, and display it in a cycle:
Circuit function description: input one's own student number (8-digit decimal number) through the key on ego1, and store it in 32-bit register; after the completion of 8-digit decimal number input, the scrolling display effect is realized.)
- 2020-12-19 16:09:10下载
- 积分：1
-
Noc
credit base network on chip(network on chip (noc))
- 2020-06-19 11:40:02下载
- 积分：1
-
UDP协议的Verilog代码
采用Verilog语法编写的UDP协议网络 能够实现UDP包的发送和接收 采用Verilog语法编写的UDP协议网络 能够实现UDP包的发送和接收 采用Verilog语法编写的UDP协议网络 能够实现UDP包的发送和接收
- 2023-04-27 15:25:03下载
- 积分：1
-
CPU流水线设计报告
说明： CPU课程设计要求以FPGA开发平台为例，分析 CPU 设计的流程与仿真。
本次开发使用的硬件描述语言是 Verilog 语言，使用的指令系统是一个以 MIPS 指令集为子集的指令系统，共 22 条指令，所用的设计仿真软件Modelsim。(CPU curriculum design requires FPGA development platform as an example to analyze the process and Simulation of CPU design.
The hardware description language used in this development is Verilog language, and the instruction system used is an instruction system with MIPS instruction set as a subset, with 22 instructions in total. The design simulation software Modelsim is used.)
- 2020-12-24 12:09:05下载
- 积分：1
-
msk_mod_demod
该程序实现最小频移键控信号的调制解调，经测试无误。(The program implements minimum shift keying signal modulation and demodulation, tested and correct.)
- 2013-10-14 23:02:39下载
- 积分：1
-
vibration-test-for-shafting-system
轴系测试程序，多通道输入输出，实现时域、频域、轴心轨迹、瀑布图等功能。(Shafting test program, multi-channel input and output, to achieve time domain, frequency domain, orbit, waterfall and other functions.)
- 2013-06-28 16:20:50下载
- 积分：1
-
bt656_decode
将嵌入式BT656格式数据解码出带行场同步信号的YCbCr422格式数据(Decoding Embedded BT656 Format Data to YCbCr422 Format Data with Field Synchronization Signa)
- 2021-01-28 10:38:35下载
- 积分：1
-
基于VHDL的UART控制器设计
UART模块的VHDL语言设计(Design of VHDL language based on UART module)
- 2017-11-13 23:56:26下载
- 积分：1
