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ppm
ppm调制的verilog代码 可实现ppm调制(ppm modulation verilog code ppm modulation)
- 2012-10-23 11:29:33下载
- 积分：1
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DW_apb_rtc
verilog实现RTC功能，可直接用于芯片开发中。(verilog achieve RTC function can be directly used for chip development.)
- 2020-12-28 16:49:01下载
- 积分：1
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GPS全球定位接收机 原理与软件实现_12378929
本书从电子技术和通信系统的角度讲解gps接收机的设计开发原理，其内容集中在用户终端，即接收机的设计原理和软件实现上。全书分为两大部分，第一部分为理论篇，第二部分为实现篇。理论篇首先对导航的基本目的进行了阐述，并由一个浅显的二维导航系统对导航信号的特点进行了推导，随后阐述了gps信号格式，同时对于直接影响接收机性能的射频前端部分做了理论分析；实现篇主要对本书实现的软件gps接收机的系统实现和源代码进行了讲解，同时作为总结，将信号处理的结果和有意义的中间变量以图示的方式给出，可以使读者有一个感性的认识，同时提升学习兴趣。.
本书适合从事卫星导航接收机研发的技术人员和卫星通信接收机研究的研究人员，尤其是从事北斗系统研发的专业人员、cdma通信系统研发人员，以及通信电子类专业的高年级本科生和研究生阅读，既可作为教学培训的教材，也可作为相关专业工程技术人员的参考资料。(This book explains the design and development principle of the GPS receiver from the perspective of electronic technology and communication system. Its content focuses on the design principle and software implementation of the user terminal, that is, the receiver. The whole book is divided into two parts. The first part is the theoretical part and the second part is the realization part. Firstly, the basic purpose of navigation is expounded, and the characteristics of navigation signal are deduced by a simple two-dimensional navigation system. Then, the format of GPS signal is expounded. At the same time, the front-end part of radio frequency which directly affects the performance of the receiver is theoretically analyzed.)
- 2019-05-05 08:54:24下载
- 积分：1
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VHDL的重要PPT资料,对初学者非常有益处
VHDL的重要PPT资料,对初学者非常有益处-VHDL important PPT information is very useful for beginners
- 2022-08-23 09:05:36下载
- 积分：1
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Xilinx ISE License
说明： Xilinx ISE License集合，包含Vivado、ise的破解license，安装ISE后loading license即可完成，最全的器件库(Xilinx ise license Collection, including Vivado and ISE cracking licenses. After ISE is installed, the loading license can be completed, which is the most complete device library.)
- 2021-01-19 23:28:43下载
- 积分：1
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VHDL数字系统设计和工程实践2，包含原理，真值表和原理图，以及VHDL源代码....
VHDL数字系统设计和工程实践2，包含原理，真值表和原理图，以及VHDL源代码.-VHDL digital system design and engineering practice, one that contains principles, truth table and schematic, as well as VHDL source code.
- 2022-08-10 05:59:32下载
- 积分：1
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sdio_slave
SDIO slave verilog code
- 2021-03-26 15:39:13下载
- 积分：1
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hssdrc IP核的可配置的通用SDRAM控制器的自适应银行…
HSSDRC IP core is the configurable universal SDRAM controller with adaptive bank control and adaptive command pipeline.
HSSDRC IP core and IP core testbench has been written on SystemVerilog and has been tested in Modelsim.
HSSDRC IP core is licensed under MIT License
- 2022-09-20 22:10:03下载
- 积分：1
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test_uart
基于fpga的uart串口通信协议，64位数据(Uart communication protocol based on fpga, 64-bit data)
- 2017-08-09 17:35:47下载
- 积分：1
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FPGA讲义适合中等以上读者，主要是FPGA的一些高级应用
FPGA讲义适合中等以上读者，主要是FPGA的一些高级应用-FPGA notes for readers more than moderate, mainly a number of advanced applications FPGA
- 2022-06-16 08:29:17下载
- 积分：1
