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mimo_dectection
mimo检测算法的FPGA实现，包括最小迫零检测算法和ML检测算法，已在ISE上仿真通过
(mimo detection algorithm for FPGA implementation, including the smallest zero forcing detection algorithm and ML detection algorithm has been simulated by ISE on)
- 2021-02-15 12:09:48下载
- 积分：1
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verilog例子，有130多个，值得参考，新手很有帮助
verilog例子，有130多个，值得参考，新手很有帮助-Verilog example, there are more than 130, it is also useful, very helpful to novice
- 2022-10-14 23:55:03下载
- 积分：1
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AVR_Core.tar
CPLD例程(语言)《Verilog HDL数字控制系统设计实例》AVR_Core.tar.gz-.rar(CPLDprogram dialogue /Verilog language design examples)
- 2011-11-12 20:43:49下载
- 积分：1
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Verilog_HDL
华为文档《硬件描述语言Verilog基础》-目录
原来搞VHDL，刚刚开始学Verilog。觉得这个入门的提纲不错，共享一下。
(Huawei Documents " basic Verilog Hardware Description Language" - the original directory engage in VHDL, just beginning to learn Verilog. Feel that the entry of the outline of a good, share some.)
- 2009-02-21 18:02:37下载
- 积分：1
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PCIeData-Link-Layer-Specifications
PCIe数据链路层的协议详解，对做PCIe接口有非常重要的指导价值。(PCIe data link layer protocol detailed, do PCIe interface very important value.)
- 2012-08-31 12:33:15下载
- 积分：1
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设计含异步清零和同步时钟使能的加法计数器
设计含异步清零和同步时钟使能的加法计数器-Clear design with asynchronous and synchronous clock so that the adder counter
- 2023-03-27 21:05:03下载
- 积分：1
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TEXIO
TEXIO study testbench passed VHDL FPGA CPLD simulation Altera quartus
- 2015-03-21 23:19:21下载
- 积分：1
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6
说明： 4位数码扫描显示电路,我们控制一个七段LED需要8个输出端口；如果要输出四位十进制数，就需要32的输出端口，这将占用大量的端口资源。采用串行扫描显示，我们只需要8+4共12个端口即可。其原理是：用一个四位的输出端控制，某一时刻只选中其中的一个LED（输出为‘1’表示选中），八位的输出端将该LED所需要显示的值输出；然后四位的输出端值改变，选中下一个LED。这样依次类推。如果选择的频率很快，达到50Hz以上，由于人眼的视觉暂留效应，看起来就像4个LED同时显示。
设计一个程序，输入四个一位十进制数，用4个LED显示出来。CLK采用频率可调信号发生器，逐渐改变频率，观察扫描频率的改变对输出效果的影响。
输入：连续脉冲，逻辑开关；输出：七段LED。
(4 digital scanning display circuit, we need to control a seven-segment LED output port 8 If you want to output four decimal numbers, you need the output port 32, which will take up a lot of ports. Serial scans showed, we need only 8 of 12 ports can be+4. The principle is: the output of four with a control, a time to select only one LED (output 1 is selected), 8 output of the LED by the need to show the value of the output then The output value of the four changes, select the next LED. This and so on. If you select the frequency rapidly, reaching more than 50Hz, as the human eye s persistence of vision effect, looks like a 4 LED display simultaneously.
Design a program, enter a decimal number four, with four LED display. CLK signal generator with adjustable frequency, gradually changing the frequency of observed changes in scan frequency effect on the output.
Input: Continuous pulse, logic switches output: seven-segment LED.)
- 2010-06-21 22:07:59下载
- 积分：1
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SPI
design and implement a digital system on the Altera NIOS board which will read an analogue input using MicroChip’s SPI MCP3202 12-Bit A/D converter. The 8 most significant bits of the converted data will be displayed on two seven segments of the NIOS development board. The sampling frequency is 20kHZ. Use a potentiometer.(design and implement a digital system on the Altera NIOS board which will read an analogue input using MicroChip' s SPI MCP3202 12-Bit A/D converter. The 8 most significant bits of the converted data will be displayed on two seven segments of the NIOS development board . The sampling frequency is 20kHZ. Use a potentiometer.)
- 2010-08-17 19:16:12下载
- 积分：1
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汉明码在调试和实现校正的原理、实现方法。
在汉明码调试中实现了纠错原理，达到更快的效果，更少的资源浪费
- 2022-03-01 01:18:26下载
- 积分：1
