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Xilinx FPGA RAM块可通过JTAG
Xilinx FPGA block RAM reconfig via JTAG
- 2022-01-25 19:09:13下载
- 积分：1
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zzlB
QUARTUSII 9.0 下的三级流水线中值滤波工程，vhdl源程序等。可用于fpga做图像预处理。(the three stage pipeline median filter project under QUARTUSII 9 , VHDL source program. which can be used by FPGA to do image preprocessing.
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- 2011-12-21 16:17:41下载
- 积分：1
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yunchengxu
说明： 内附几十种小程序，有状态机、比较器、波形发生器、乘法器、加法器、步进电机控制器等，希望大家能用的上。(Containing dozens of small programs, for reference，This is about FPGA,a tool ,we can study,but in ourselves.)
- 2010-04-29 16:00:25下载
- 积分：1
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fffffff
如上图所示， Rst是低电平有效的系统复位信号，Clk是时钟信号。AB[5：0]是地址信号，DB[7：0]是数据信号，wr是低电平有效的写信号。start是启动信号。
模块中有一个64x8的双端口的存储器。系统复位结束后，可以通过AB、DB和wr信号向同步存储器写入数据。当写入64个数据后，给出一个Clk周期宽度的脉冲信号start，则系统从存储器0地址处开始读出数据，读出的8位数据从低位开始以3位为一组，每个时钟周期输出一组，即第一个时钟周期输出[2：0]位，第二个时钟周期输出[5：3]位，第三个周期输出1地址的[0]位和0地址的[7：6]位，直至将存储器中64x8数据全部输出。若最后一组不足三位，则高位补0。
(As shown above, Rst is an active-low system reset signal, Clk is a clock signal. AB [5: 0] is the address signal, DB [7: 0] is the data signal, wr write signal is active low. start is the start signal. Module in a dual port memory of 64x8. After the reset, you can write data to the synchronous memory by AB, DB and wr signals. When data is written to 64, given the width of a pulse signal Clk cycle start, the system begins to read the memory address 0, 8 data read out a low starting with three as a group, each clock outputs a set period, which is the first clock cycle of the output [2: 0] bits, the second clock cycle output [5: 3] position, the third cycle of the output of an address [0] and 0 address [7 : 6] bit, until all the data in memory 64x8 output. If the last group of less than three, the high 0s.)
- 2020-11-04 20:39:51下载
- 积分：1
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20181060261-李康_3
说明： 秒表的实现，有暂停清零功能，Quartus II(Stopwatch realization, has the pause clear function)
- 2020-12-26 15:56:03下载
- 积分：1
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HARQ
HARQ技术研究，以喷泉码为研究对象，结合LDPC纠错码而研究的。(HARQ technology research to fountain codes for the study, and research combined with LDPC error correction code.)
- 2015-05-21 16:54:15下载
- 积分：1
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EMI
说明： Simetrix EMI滤波器设计，实际测试有效果。(Simetrix EMI filter design, the actual test results are effective.)
- 2019-10-01 22:28:37下载
- 积分：1
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ldpc-for-fpga-decoding
ldpc译码算法的matlab实现，码长960，码率1/2,完全模拟fpga硬件实现语言，量化处理。(ldpc decoding using matalb,code length 960,code rate 1/2)
- 2021-04-12 21:38:56下载
- 积分：1
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alu
说明： VHDL实现的算术逻辑计算单元（ALU），包括modersim测试文件，即仿真结果。(VHDL implementation of the arithmetic logic calculation unit (ALU), including modersim test file, the simulation results.)
- 2011-03-26 21:18:01下载
- 积分：1
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讲解用FPGA及其他芯片组成视频处理的电路设计和PFGA的程序的实现...
讲解用FPGA及其他芯片组成视频处理的电路设计和PFGA的程序的实现-Explain the use of FPGA and other video processing chips of the circuit design and FPGA realization of the procedure
- 2022-06-12 17:12:42下载
- 积分：1
