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shift_reg
Shift reg in vhdl, a first example to start
- 2011-03-27 10:35:25下载
- 积分：1
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NIOS_TIMER
很不错的资源哦，这是我在实验室当年总结的关于nios timer的程序段(nios timer)
- 2014-06-18 09:13:42下载
- 积分：1
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system
清华大学电子课程设计：Verilog，QuartusII可正确运行，可下载到FPGA上，完成远程通信的整体任务，PC发数据，键盘输入运算符与运算数计算将结果显示在数码管上并返回给PC机，需异步串口调试软件(Verilog, QuartusII run correctly, can be downloaded to the FPGA, to complete the overall task of remote communication, PC send data, keyboard operators and operands calculation displays the results in digital tube and returned to the PC, to be asynchronous serial debugging software)
- 2020-08-16 23:38:25下载
- 积分：1
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在QuartusII运用ＡＨＤＬ语言，首先设计出PN发生器来产生一个11位的数据流在整个周期内有效数据有 =2047位；再设计状态机用来检测串行数据流中的序列。...
在QuartusII运用ＡＨＤＬ语言，首先设计出PN发生器来产生一个11位的数据流在整个周期内有效数据有 =2047位；再设计状态机用来检测串行数据流中的序列。运用两个个计数器分别对PN码计数以及序列出现的次数计数。改变ＰＮ码结构可以作为通用数列检测器-QuartusII use in AHDL language, the first PN generator designed to generate a data stream 11 throughout the cycle has an effective data = 2047 re-designing the state machine used to detect the serial data stream in sequence. The use of two counters were counting on the PN code, as well as counting the number of sequences occur. Changes in the structure of PN code series can be used as general-purpose detector
- 2023-03-11 09:20:03下载
- 积分：1
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crc_verilog_xilinx
crc校验，非常好用，是从Xilinx的IP演化来的(crc脨 拢 脩茅 拢 卢 脟 鲁 拢 潞 脙脫脙 拢 卢 脢脟)
- 2021-03-01 11:49:34下载
- 积分：1
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VHDLrefencebook
doulos公司出的VHDL学习工具，非常易学易懂！~(doulos company out of the VHDL learning tool, very easy to understand! ~)
- 2016-10-09 15:45:57下载
- 积分：1
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regheap
该模块实现一个寄存器堆的操作，其中前16个仅主机能写，规给为32-bit×32。后16个仅Micorblaze能写。读取没有限制。如果双方同时对同一地址进行读写操作，读回的数将是全1。(This module implement a register file of the operation, of which the first host 16 is only able to write rules to the 32-bit × 32. Micorblaze only 16 after the write. There is no limit to read. If the two sides at the same time to read and write operations to the same address, read back would have been a full one.)
- 2009-12-10 15:39:59下载
- 积分：1
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数字电子钟
数字电子钟用自拍图像代替了内置图像的石英制作
- 2022-02-01 06:03:40下载
- 积分：1
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DDR2_hardcore_userguide
xillinx Spartan6 FPGA DDR 接口设计指南(xillinx Spartan6 FPGA DDR Interface Design Guidelines)
- 2009-11-23 10:18:28下载
- 积分：1
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Nut
UG二次开发，课程作业，研究生，学习，初学者，打孔，复杂体，阵列
UG C program，homework，student，study，first，hole，complex，many(
UG C program，homework，student，study，first，hole，complex，many)
- 2015-01-15 12:26:29下载
- 积分：1
