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UART_RX_
说明： fpga串口的发送程序基于verilog语言拿走不用谢。(The sending program of FPGA serial port is based on Verilog language.)
- 2020-06-18 04:00:01下载
- 积分：1
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add_verilog
2位全加器，实现全加器的功能，有近位的加法，输出也有近位，还有testbench,进行验证，验证通过(Two full adders, to achieve full adder function, nearly bit adder, there are nearly bit output)
- 2014-05-14 18:56:33下载
- 积分：1
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VHDL version of the C8051 core (C8051). Evatronix company s IP core
VHDL版的C8051核(C8051).evatronix公司的IP核-VHDL version of the C8051 core (C8051). Evatronix company s IP core
- 2022-09-22 12:10:03下载
- 积分：1
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sanjose_hdlcon
FFT implementation using C program
- 2014-02-11 21:01:40下载
- 积分：1
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vending-machine
用Verilog实现自动售货机功能，代码较初级。易懂，内含test文件。(Automatic vending machines function with Verilog code than the primary. Understandable, containing test files.)
- 2013-11-30 20:25:34下载
- 积分：1
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FPGA中嵌入8051的核 并且实现控制128*64的液晶显示
FPGA中嵌入8051的核 并且实现控制128*64的液晶显示-FPGA embedded in 8051 and to achieve control of the nuclear 128* 64 LCD
- 2023-05-15 17:55:03下载
- 积分：1
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本文是自已写的电子密码锁的详细开发过程，用的是Modelsim进行仿真实现，打开文档lzp...
本文是自已写的电子密码锁的详细开发过程，用的是Modelsim进行仿真实现，打开文档lzp-This article is written in their own electronic locks detailed development process, using a ModelSim simulation achieved, open the document lzp
- 2022-01-25 15:10:58下载
- 积分：1
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bt656_to_yuv422
从bt656数据流中提取出同步信号, 适合于搞fpga/cpld开发调式(bt656 internel sync to extern sync singal，
bt656 internel sync to extern sync singal)
- 2021-03-06 11:19:30下载
- 积分：1
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ddr2_controller
DDR2控制器设计原码,可以在FPGA上测试通过,并对外部的ddr memory进行读写访问.(DDR2 controller design of the original code, can be tested through the FPGA, and external ddr memory read and write access.)
- 2010-02-23 09:16:50下载
- 积分：1
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Verilog LDPC码
说明： LDPC码的BP译码verliong程序(BP decoding veriong program of LDPC code)
- 2020-03-03 18:14:12下载
- 积分：1
