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imports
说明: displayport 参考设计,可以对比自己工程做验证,另有参考设计XAPP1178未找到,采用方案为DP159 + Artix7 FPGA(xilinx displayport sink design)
- 2021-01-11 16:58:50下载
- 积分:1
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VHDLFIFO
用Verilog 写一个8x16 的FIFO,完成先入先出的功能,并且在FIFO读空时输出EMPTY
有效信号,读指针RP 不再移动;FIFO 写满时输出FULL 有效信号,并且即使WR 有效也
不再向存储单元中写入数据(写指针WP 不再移动)。
(NO)
- 2020-09-20 20:17:51下载
- 积分:1
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DDR_SDRAM_verilog
说明: DDR(双速率)SDRAM控制器参考设计verilog代码,可以直接用的,很好的(DDR (double rate) SDRAM controller reference design Verilog code, can be directly used, very good)
- 2021-03-13 16:39:24下载
- 积分:1
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Verilog--image-sample
基于Verilog的图像采集、处理和存储程序,初学者参考,高手绕道。(Verilog-based image acquisition, processing and storage procedures, beginners reference, master bypass.)
- 2021-04-16 11:48:54下载
- 积分:1
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vhdlcoder
VDHL的简单DEMO演示,有利于初学者学习使用(VDHL simple demo DEMO will help beginners learn to use)
- 2008-01-16 15:44:44下载
- 积分:1
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shuzizhong3
数字钟VHDL软件设计,包含多种功能,报时,12,24切换,调时(The design of VHDL digital clock software, including a variety of functions, timer, 12,24 switch, adjustable)
- 2016-05-27 11:41:22下载
- 积分:1
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dr6—ise-F
用FPGA开发板的按键作为电子表的时间初值设置控制信号,数码管当前时间值输出。用按键选择分别输出:分、秒、1/10秒。(With FPGA development board button, as the time value of the electronic table, set the control signal, digital tube current time value output. Select output by buttons: minutes, seconds, and 1/10 seconds.)
- 2017-10-11 21:19:55下载
- 积分:1
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waveform-generator-o-VHDL-program
实现4种常见波形正弦、三角、锯齿、方波(A、B)的频率、幅度可控输出(方波
--A的占空比也是可控的),可以存储任意波形特征数据并能重现该波形,还可完成
--各种波形的线形叠加输出。
(Achieve the four kinds of common sine wave, triangle, sawtooth, square wave (A, B) the frequency and amplitude controlled output (square wave- A duty cycle is controlled), can store arbitrary waveform feature data and can to reproduce the waveform, it can perform- all kinds of linear superposition of the output waveform.)
- 2009-10-08 09:56:59下载
- 积分:1
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04_uart_test
说明: 基于FPGA,用verilog hdl语言实现串口收发实验(Based on FPGA, using Verilog HDL language to achieve serial port transceiver experiment)
- 2021-03-14 13:43:49下载
- 积分:1
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verilog计数器
verilog计数器,属于数字电子技术实验入门的资料。
- 2023-05-18 05:25:04下载
- 积分:1