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Case-statement-described-4-1-Mux
用case 语句描述的4 选1 Mux 源码程序，好用(-4 with a case statement described 1 Mux source program, easy to use)
- 2012-10-21 09:47:32下载
- 积分：1
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lesson1
eda的入门学习课件，老师不错，内容页挺好的(eda learning files)
- 2012-12-14 22:39:31下载
- 积分：1
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ces_svtb_2011.12
synopse sv培训lab，是学习systemverilog非常好的资料，放心下载。(synopsis sv training lab)
- 2021-04-19 11:18:51下载
- 积分：1
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sm4
VHDL实现国家SM4加密算法（ECB）模式 (VHDL to achieve national SM4 encryption algorithm (ECB) mode)
- 2020-08-12 06:58:26下载
- 积分：1
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最新的ATA
最新的ATA-六总线协议源代码参考，实现DMA,PIO模式，可挂CDROM,IDE硬盘，CF卡．-the latest ATA-6 bus protocol source code reference, achieving DMA, PIO Mode, can be linked to CDROM, IDE hard drive, CF card.
- 2022-04-11 09:20:29下载
- 积分：1
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FPGAAD9854DDS
FPGA测序和DDS产生各种波形程序，用Atral器件开发(FPGA sequencing and DDS generate various waveform programs.)
- 2018-11-14 22:07:21下载
- 积分：1
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IRIG_DC_Decoder
IRIG_B解码器，直接解码IRIG_B DC(IRIG_B decoder)
- 2021-04-09 16:58:59下载
- 积分：1
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add_verilog
2位全加器，实现全加器的功能，有近位的加法，输出也有近位，还有testbench,进行验证，验证通过(Two full adders, to achieve full adder function, nearly bit adder, there are nearly bit output)
- 2014-05-14 18:56:33下载
- 积分：1
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Synthesizable model of Atmel Application of ATmega103 mi crocontroller. (VHDL IP...
Synthesizable model of Atmel ATmega103 microcontroller. (VHDL IP)-Synthesizable model of Atmel Application of ATmega103 mi crocontroller. (VHDL IP)
- 2022-02-12 19:56:59下载
- 积分：1
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VHDL，verilog串并转换源程序
Xilinx公司参考资料
VHDL，verilog串并转换源程序
Xilinx公司参考资料-VHDL, verilog Series and conversion company Xilinx reference source
- 2023-04-26 17:40:03下载
- 积分：1
