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FIFO程序，适用FPGA仿真的代码，有一定的价值
FIFO程序，适用FPGA仿真的代码，有一定的价值-FIFO
- 2022-08-10 12:12:14下载
- 积分：1
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A VEILOG HDL procedures, can be applied directly,
一个VEILOG HDL程序，可以直接应用，-A VEILOG HDL procedures, can be applied directly,
- 2023-02-01 17:30:03下载
- 积分：1
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RS232 data transmitter, suitable for beginners VHDL reference
RS232数据发送器,适合于VHDL的初学者参考-RS232 data transmitter, suitable for beginners VHDL reference
- 2022-03-15 09:13:00下载
- 积分：1
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译码器，将八位输出转换为七段译码显示，相当于7448驱动译码管...
译码器，将八位输出转换为七段译码显示，相当于7448驱动译码管-Decoder, the 8 output is converted to seven segment decoding shows that the equivalent of 7448
- 2022-05-30 05:04:27下载
- 积分：1
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- 2023-04-14 01:30:04下载
- 积分：1
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在quartus下搭建的数字锁相环
在quartus下搭建的数字锁相环，能实现频率自动跟踪。(The digital phase-locked loop built under quartus can realize automatic frequency tracking.)
- 2020-06-21 01:00:02下载
- 积分：1
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32_lvds_test
Xilinx 公司Spartan-6系列FPGA实现LVDS，带Modelsim仿真文件，已综合。(Xilinx Spartan-6 Series FPGA implements LVDS with Modelsim simulation file, which has been synthesized.)
- 2020-11-30 20:59:27下载
- 积分：1
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src
yuv444 与yuv422相互转换verilog语言(yuv444 to yuv422)
- 2021-01-20 14:38:41下载
- 积分：1
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吠陀乘数
吠陀乘数
- 2022-01-31 06:52:01下载
- 积分：1
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Top module name : SHIFTER (File name : SHIFTER.v)
2. Input pins: SHIFT [3:0],...
Top module name : SHIFTER (File name : SHIFTER.v)
2. Input pins: SHIFT [3:0], IN [15:0], SIGN, RIGHT.
3. Output pins: OUT [15:0].
4. Input signals generated from test pattern are latched in one cycle and are
synchronized at clock rising edge.
5. The SHIFT signal describes the shift number. The shift range is 0 to 15.
6. When the signal RIGHT is high, it shifts input data to right. On the other hand, it
shifts input data to left.
7. When the signal SIGN is high, the input data is a signed number and it shifts with
sign extension. However, the input data is an unsigned number if the signal SIGN
is low.
8. You can only use following gates in Table I and need to include the delay
information (Tplh, Tphl) in your design.
- 2022-04-13 06:40:15下载
- 积分：1
