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counter-with-T_FF
This is counter with T_FF.
- 2016-03-26 16:36:05下载
- 积分：1
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用NiosII实现的数字钟，经过本人测试运行正常，开发环境：QuartusII6.0和NiosII IDE6.0...
用NiosII实现的数字钟，经过本人测试运行正常，开发环境：QuartusII6.0和NiosII IDE6.0-NiosII achieved with digital clock, after I run the normal tests, development environment: QuartusII6.0 and NiosII IDE6.0
- 2023-04-12 03:05:04下载
- 积分：1
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multiplay
连乘,乘法可以用简单的for循环，我这里用的是移位寄存器来做，而且是用来两个移位寄存器(this is a tool that function is multiplay,it use a special way to do multiplay .it will teach you the how to use labview )
- 2015-02-04 20:44:16下载
- 积分：1
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cadence verilog lanaguage and simulation course
cadence verilog lanaguage and simulation course
- 2022-03-03 00:45:22下载
- 积分：1
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卡内基梅陇大学verilog课程讲义-unlocked
说明： verilog讲义
卡内基梅陇大学verilog课程讲义-unlocked
卡内基梅陇大学verilog课程讲义-unlocked(Verilog Course Lectures at Carnegie Mellon, University Verilog Course Lectures at Carnegie Mellon University Verilog Course Lectures at Carnegie Mellon University)
- 2020-06-20 18:00:02下载
- 积分：1
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VENDTEST
此为实现第14.7.9章所需的激励文件
该代码为门级RTL描述。(Stimulus file to verify Section 14.7.9
the functionality of
gate vs. RTL description.)
- 2011-08-11 15:07:16下载
- 积分：1
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GPSDECODE
完成GPS的IRIG_B码解码，已经模块化，并且有详细的中文注释(Completed the GPS IRIG_B of decoding modular, and there are detailed notes in Chinese)
- 2021-04-07 16:09:01下载
- 积分：1
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In the Altera chip 2C35F672 platform FFT procedures DSPBuilder5.0, generated Ver...
在Altera芯片2C35F672平台上的FFT程序，采用DSPBuilder5.0，生成Verilog文件。开发环境：QuartusII5.0。-In the Altera chip 2C35F672 platform FFT procedures DSPBuilder5.0, generated Verilog file. Development Environment: QuartusII5.0.
- 2022-03-16 05:08:13下载
- 积分：1
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CHANNEL_ESTIMATION_PROJECT
基于 quartus 2 的 lte 信道估计verilog hdl代码 只有功能仿真 时序仿真自己加sdc文件并且调整testbench的clk才能做出来(Estimated Verilog HDL code based Quartus lte channel only functional simulation timing simulation plus sdc file and adjust the testbench clk to do it)
- 2013-04-22 19:29:00下载
- 积分：1
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I2C配置tvp5150用VHDL写的
I2C配置tvp5150用VHDL写的 -I2C configuration tvp5150 written using VHDL
- 2023-05-02 14:30:04下载
- 积分：1
