网站首页

UART的源（格版）

于 2022-10-19 发布文件大小:85.10 kB

 0  171

下载积分: 2 下载次数: 1

我要下载

代码说明：

UART 源码 (lattice version)-UART source (lattice version)

下载说明：请别用迅雷下载，失败请重下，重下不扣分！

发表评论

0 个回复

MAX+plus II编译的模30加法计数器，简单的与非门组成！
MAX+plus II编译的模30加法计数器，简单的与非门组成！-MAX+ Plus II compiler module adder 30 counters, a simple composition with the non-door!

2022-04-18 02:27:03下载

积分：1
Verilog HDL的PLI子程序接口，用于与用户C程序在2个方向上传输数据，可用xilinx ISE，quartusii或modelsim仿真，...
Verilog HDL的PLI子程序接口，用于与用户C程序在2个方向上传输数据，可用xilinx ISE，quartusii或modelsim仿真，-Verilog HDL PLI subroutine interfaces, for C program with the user in the direction of two transmission of data, available xilinx ISE. quartusii or modelsim simulation,

2022-03-21 07:59:28下载

积分：1
FFT2
适用于NIOS II的1024点FFT C算法( 1024-point FFT C algorithm for NIOS II)

2010-12-04 15:32:44下载

积分：1
Interface design between microprocessor and cpld ,suit for IC design and applica...
cpld与单片机接口设计,利于电子设计及应用- Interface design between microprocessor and cpld ,suit for IC design and application

2022-03-25 22:52:32下载

积分：1
ROM建立平方电路
A ROM to build a squaring circuit

2022-08-07 16:45:22下载

积分：1
Harris-algorithm-based-on-FPGA
在利用FPGA的并行处理能力应对高速数据和去做复杂的数据处理时，对一些较为复杂或者重复性工作模块多的情况下，算法资源就需要进行预评估。有效的资源预评估不仅可以在芯片选型上有益，还可以对程序有较详细的估计，在硬件不变的前提下能够选择更好的算法优化。本文着重在Harris算法在FPGA的实现以及在移植之前对其占用的FPGA资源进行预评估。(Response to high-speed data and do complex data processing in the FPGA parallel processing capabilities, to cope with some of the more complex or repetitive tasks module，it is necessary to pre-assessment algorithm resources. Resources pre-assessment can not only be useful in the chip selection, but also be a more detailed estimate of the program to be able to choose a better algorithm optimization in the same premise hardware. This article focuses on the pre-assessment in the Harris algorithm in the FPGA implementation and its FPGA resources occupied prior to transplantation.)

2013-02-28 15:41:39下载

积分：1
sd_ctrl
利用verilog实现对SD卡的控制，可以实现对SD卡的读写。(Verilog SD)

2020-12-27 21:49:03下载

积分：1
which I have recently bought a CPLD Development Board VHDL source code accompani...
这是我最近买的一套CPLD开发板VHDL源程序并附上开发板的原理图,希望对你是一个很好的帮助!其中内容为:8位优先编码器,乘法器,多路选择器,二进制转BCD码,加法器,减法器,简单状态机,四位比较器,7段数码管,i2c总线,lcd液晶显示,拨码开关,串口,蜂鸣器,矩阵键盘,跑马灯,交通灯,数字时钟.-which I have recently bought a CPLD Development Board VHDL source code accompanied the development of the plate diagram, You hope to be a good help! which states : eight priority encoder, multipliers, multi-path selectors, BCD binary switch, adder, subtraction device, the simple state machine, four comparators, seven of the digital control, i2c bus, lcd LCD allocated code switches, serial port, the buzzer sounded, matrix keyboards, Bomadeng, traffic lights, Digital Clock.

2022-02-20 05:51:18下载

积分：1
11_sdi1in_hdmi_out_proc
FPGA SDI 输入，HDMI输出例程(FPGA SDI_IN,HDMI_OUT)

2018-07-25 16:30:52下载

积分：1
Altera DE2板专用CCD驱动器
altera DE2 实验板专用 CCD驱动-altera DE2 board dedicated CCD driver

2022-02-10 05:21:46下载

积分：1

696516资源总数
106459会员总数
0今日下载

UART的源（格版）

0 个回复

热门标签

热门下载