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traffic
说明： 模拟交通灯
verilog CPLD
EPM1270
源代码(Simulation of traffic lights verilog CPLDEPM1270 source code)
- 2008-10-30 23:12:20下载
- 积分：1
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FPGA-IMPLEMENTATIONS-OF-THE-DES
FPGA based design and Implementation of Advanced Encryption Standard
- 2015-07-20 23:33:11下载
- 积分：1
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M_M
此为数学形态滤波器消燥的代码，用于一维信号，涉及一个具体的例子，需要的话可以自己修改，修改相应的结构元素。(This is a mathematical morphology filter away dry code, used to one dimensional signal, involving a concrete example, necessary can change ourselves, change the structure of the corresponding elements)
- 2013-08-29 21:36:37下载
- 积分：1
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code
代码文件夹：
ARVI_FSM.v为顶层文件，用于模拟时用。
dataHex.dat 为模拟输入文件（只有10行，象征的意思。实际我们模拟时，dataHex.dat文件足有1个多GB）
dataFormat.dat为输入文件对应的带格式的文件
使用modelsim模拟时，将dataHex.dat名字改为CPUContext.txt
结果:
result.txt
(Code folder: ARVI_FSM.v for top-level documents used for the simulation. dataHex.dat for analog input files (only 10 line, the meaning of the symbol. actual simulation we, dataHex.dat documents have more than one full GB) dataFormat.dat for the input file the corresponding file with modelsim simulation used to dataHex.dat name to CPUContext.txt results: result.txt)
- 2009-06-21 19:14:37下载
- 积分：1
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FIR
说明： 一个1MHz的FIR低通滤波器。
① 时钟信号频率16MHz;
② 输入信号位宽8bits，符号速率16MHz；
③ 要求在Matlab软件中进行FIR滤波器浮点和定点仿真，并确定FIR滤波器抽头系数；
④ 写出测试仿真程序。(A 1MHz FIR low pass filter.
(1) The clock signal frequency is 16MHz;
(2) The input signal has a bit width of 8 bits and a symbol rate of 16 MHz;
(3) Floating-point and fixed-point simulation of FIR filter is required in Matlab software, and tap coefficients of FIR filter are determined.
(4) Write the test simulation program.)
- 2019-06-19 21:47:13下载
- 积分：1
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fht_latest.tar
FAST HADAMARD TRANSFORM VERILOG FOR IMAGE PROCESSING
- 2013-08-19 13:47:40下载
- 积分：1
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Quartus_II部分实例
说明： 38译码器，D触发器，全加器，计数器，抢答器，优先编码器，111序列检测器，并行输入转串行输出(poor English.
38 decoder, D trigger, full adder, counter, scrambler, priority encoder, 111 sequence detector, parallel input to serial output)
- 2020-05-18 12:06:54下载
- 积分：1
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XC3S700_UART_Test
红色飓风3S700AN开发板UART测试例程(Red Hurricane 3S700AN development board UART test code)
- 2013-07-12 00:34:31下载
- 积分：1
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sd_models_verilog
测试过可用的SD仿真模型，VERILOG语言(SD card simulation modle, test OK)
- 2021-02-26 20:09:37下载
- 积分：1
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24x24-booth
可用的24位x24位的booth乘法器的verilog代码(24X24 booth muplily)
- 2011-06-09 17:59:26下载
- 积分：1
