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Verilog的135个经典设计实例.使你工作使用学习中，会有很大帮助，各种典型案例(135 classic Verilog design examples. Make your work with the study, will be of great help, of various typical cases
)
- 2014-03-19 10:55:14下载
- 积分：1
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verilog 写的 “梁祝”乐曲演奏电路
verilog 写的 “梁祝”乐曲演奏电路-verilog wrote " The Butterfly Lovers" music concert circuit
- 2022-02-03 08:31:54下载
- 积分：1
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HDMI接口编解码传输模块ASIC设计_刘文杰
? 熟悉IIC协议总线协议，采用IIC总线对图像采集传感器寄存器进行配置，并转换为RGB565格式。
? 利用异步FIFO完成从摄像头输出端到SDRAM 和SDRAM 到VGA 接口各跨时钟域信号的传输和处理。
? 利用 SDRAM 接口模块的设计，实现了刷新、读写等操作；为提高SDRAM 的读写带宽，均采用突发连续读写数据方式；并采用乒乓操作实现 CMOS 摄像头与VGA的帧率匹配。
? 利用双线性插值方法实现对图像640×480到1024×768的放大操作。
? 完成VGA显示接口设计。(Familiar with IIC protocol bus protocol, IIC bus is used to configure the register of image acquisition sensor and convert it into RGB565 format.
Asynchronous FIFO is used to transmit and process signals across clock domain from camera output to SDRAM and SDRAM to VGA interface.
With the design of SDRAM interface module, refresh, read and write operations are realized. In order to improve the read and write bandwidth of SDRAM, burst continuous read and write data mode is adopted, and table tennis operation is used to achieve frame rate matching between CMOS camera and VGA.
The bilinear interpolation method is used to enlarge the image from 640*480 to 1024*768.
Complete the VGA display interface design.)
- 2020-06-25 04:00:02下载
- 积分：1
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controller
说明： alu control 控制 部件
alu control 控制 部件(alu control)
- 2010-04-30 10:55:26下载
- 积分：1
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hard
在Quartus中，利用FPGA例化的存储器实现程序的BOOTLOADER的搬移(In Quartus, the use of FPGA case of memory to achieve the program' s move BOOTLOADER)
- 2020-09-27 20:17:46下载
- 积分：1
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jtag
verilog jtag源码及原理，还有debug模块。边界扫描等(verilog jtag source and principle, as well as debug module. Boundary-Scan, etc.)
- 2021-04-27 14:18:44下载
- 积分：1
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基于basys3的推箱子游戏
基于FPGA的游戏实例，开发板为Xilinx的basys3，VGA显示(Basys3, VGA Display of Xilinx Development Board Based on Game Example of FPGA)
- 2021-03-12 13:09:25下载
- 积分：1
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AES 128 Crypto Core
Mini AES
Advanced Encryption Standard (AES) implementation with small area/resources utilization.
Features
- Encryption and Decryption unit in single core.
- 2023-01-28 07:05:04下载
- 积分：1
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Triscend supports the use of the Model Technology ModelSim logic simulator for V...
Triscend supports the use of the Model Technology ModelSim logic simulator for VHDL simulation of
designs implemented in the Configurable System Logic (CSL) portion of a Triscend device.
- 2023-07-10 18:40:02下载
- 积分：1
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1路视频光端机的接收端，VHDL源码，使用全FPGA芯片的硬件，内建解帧、时钟、DESERDES...
1路视频光端机的接收端，VHDL源码，使用全FPGA芯片的硬件，内建解帧、时钟、DESERDES-PDH a video of the receiving end, VHDL source code, use the whole FPGA chip hardware, built-in framing, clock, SERDES
- 2022-04-30 11:01:06下载
- 积分：1
