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quartus工具入门文档,altera公司官方软件翻译全文。
quartus工具入门文档,altera公司官方软件翻译全文。-tool for quartus entry documents, altera company official translation of the full text of the software.
- 2022-05-25 20:37:44下载
- 积分:1
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divider_latest.tar
floating point divider
- 2009-11-03 11:23:16下载
- 积分:1
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1、 利用FLEX10的片内RAM资源,根据DDS原理,设计产生正弦信号的各功能模块和顶层原理图; 2、 利用实验板上的TLC7259转换器,将1中得到的正弦信...
1、 利用FLEX10的片内RAM资源,根据DDS原理,设计产生正弦信号的各功能模块和顶层原理图; 2、 利用实验板上的TLC7259转换器,将1中得到的正弦信号,通过D/A转换,通过ME5534滤波后在示波器上观察; 3、 输出波形要求: 在输入时钟频率为16KHz时,输出正弦波分辨率达到1Hz; 在输入时钟频率为4MHz时,输出正弦波分辨率达到256Hz; 4、 通过RS232C通信,实现FPGA和PC机之间串行通信,从而实现用PC机改变频率控制字,实现对输出正弦波频率的控制。-a use FLEX10-chip RAM resources, in accordance with DDS principle, design sinusoidal signal generated by the top-level functional modules and schematics; 2, the experimental board TLC7259 converters, will be a sinusoidal signal, the D/A conversion, after filtering through the ME5534 oscilloscope observation; 3, the output waveform requirements : the input clock frequency of 16KHz, sine wave output resolution of 1Hz; the input clock frequency of 4MHz, the sine wave output resolution of 256Hz; 4, RS232C communications, FPGA and PC serial communications between in order to achieve PC-frequency control characters, the realization of sine wave output frequency control.
- 2022-01-25 19:12:14下载
- 积分:1
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是vhdl语言,在fpga开发板上实现十进制技术(7段数码管显示),包括复位,清零,计数使能。...
是vhdl语言,在fpga开发板上实现十进制技术(7段数码管显示),包括复位,清零,计数使能。-Is the VHDL language, in the FPGA development board realize decimal technology (7 digital tube display), including reset, cleared, counting enable.
- 2022-03-20 12:25:41下载
- 积分:1
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频率计实验程序代码
说明: XC7A35TCSG324-1的Verilog频率计程序,支持十分频,支持切换内外信号输入(Verilog frequency meter program of xc7a35tcsg324-1 supports decadal frequency division and switching internal and external signal input)
- 2019-12-24 13:40:45下载
- 积分:1
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1_Carm
经典的OV5642的verilog驱动程序(Verilog Driver of Classic OV5642)
- 2019-03-19 13:38:29下载
- 积分:1
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0 2
说明: 基于labVIEW,控制电机等工作实例,程序基本完整(Based on labVIEW, control motor and other working cases, the program is basically complete)
- 2018-01-24 09:09:20下载
- 积分:1
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xge_mac_latest.tar
Ethernet 10GE MAC 以太网10G的MAC Verilog代码实现(Ethernet 10GE MAC)
- 2010-07-31 10:04:20下载
- 积分:1
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det
double edfe trigger d latch
- 2014-01-07 19:55:29下载
- 积分:1
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使用从Digilent Spartan3E板VGA接口。LabVIEW VI
VGA interface using Spartan3E board from DIGILENT.Labview .vi
- 2023-02-15 00:10:04下载
- 积分:1