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24小时计时时钟
实现24小时计时，因为位数不够，这里是12进位，可自行调整进位数(Realize 24-hour timing, because the number of digits is not enough, here is 12 carry, you can adjust the carry number by yourself.)
- 2020-06-23 19:40:01下载
- 积分：1
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Electronicorgan
利用VHDL编写的电子琴发生器，以简单的演奏电路论文(Electronic organ prepared using VHDL generator to perform a simple circuit Papers)
- 2009-03-06 08:52:10下载
- 积分：1
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A4_Oscilloscope_Top
数字示波器实验，利用AD、DA和VGA三个外设来实现简易示波器，DA外设发送正弦波给AD外设，AD外设解析成数字信号将数据送给VGA外设进行显示。在VGA上可以看到DA外设发送的波形、波形频率和波形峰峰值。(In the experiment of digital oscilloscope, AD, DA and VGA are used to realize simple oscilloscope. DA peripheral transmits sine wave to AD peripheral. AD peripheral resolves into digital signal and sends data to VGA peripheral for display. The waveform, waveform frequency and peak value of DA peripheral can be seen on VGA.)
- 2019-03-13 10:45:10下载
- 积分：1
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turbo_encoder
在赛灵思的FPGA上实现turbo码的编码程序,使用Verilog语言实现。(Implemented on Xilinx FPGA in the turbo coding principle, the use of Verilog language.)
- 2021-04-19 09:38:51下载
- 积分：1
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Of PCM
对PCM编码的多路复用与解复用程序，VerilogHDL源程序-Of PCM-encoded multiplexing and demultiplexing process, VerilogHDL source
- 2022-02-05 07:01:51下载
- 积分：1
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gmsk
产生高斯最小相移键控信号的阐述仿真，包括调制解调、信道模型等。(Simulation program to realize GMSK transmission system)
- 2020-11-14 19:49:42下载
- 积分：1
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prj_ex_5
自动化仿真平台的搭建使用代码，经过具体的仿真和优化，发现代码完全可用(The automated simulation platform is built using code, and after specific simulation and optimization, it is found that the code is fully available)
- 2017-09-21 15:11:33下载
- 积分：1
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UART
说明： 串口通信vivado实现，带有仿真文件，可实现数据收发(the uart program based on vivado)
- 2020-07-02 16:15:57下载
- 积分：1
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carry_lookahead_add4
4位的超前进位加法器，门级电路连接得到，verilog代码实现(4-bit look-ahead adder, gate-level circuit)
- 2011-10-18 21:40:20下载
- 积分：1
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altera DE1 SD_CARD带写入一个扇区功能的程序，已确认成功，下载直接运行就可以看效果...
altera DE1 SD_CARD带写入一个扇区功能的程序，已确认成功，下载直接运行就可以看效果-altera DE1 SD_CARD with a sector write function procedures, has confirmed the success of running can be downloaded directly watch the effect of
- 2022-04-16 19:05:08下载
- 积分：1
