-
Advanced-FPGA-Design
高级FPGA设计__结构、实现和优化,中文翻译版(Advanced FPGA Design- Architecture, Implementation, and Optimization)
- 2021-04-01 11:09:08下载
- 积分：1
-
FM_T
一个简单的FM调制模块，FM发射，用Verilog编写，基于Xilinx SPARTAN6 XC6LX9开发(A simple FM modulation modules for FM transmitter, using Verilog prepared, based on XILINX SPARTAN6 XC6LX9 Development)
- 2020-11-25 20:19:32下载
- 积分：1
-
rfid_re
VHDL实现 DDS。大家共享吧，一起学习，一起进步(VHDL realize DDS. U.S. to share it with learning, with progress)
- 2008-05-16 15:12:13下载
- 积分：1
-
AHBtoAPB
AHBtoAPB设计基于AMBA总线协议的APB Bridge设计(AHB to APB designThe AHB to APB bridge interface is an AHB slave. When accessed (in normal operation or system test) it initiates an access to the APB.)
- 2012-01-30 12:47:15下载
- 积分：1
-
Verilog code for RS
Verilog code for RS-(255,239) encoder.
- 2022-02-02 19:13:13下载
- 积分：1
-
交织和解交织模块，采用矩阵交织方式，且有两套并行存储器，可以实现连续数据流操作，不会有数据滞留和丢失...
交织和解交织模块，采用矩阵交织方式，且有两套并行存储器，可以实现连续数据流操作，不会有数据滞留和丢失-Intertwined intertwined reconciliation module, interwoven matrix approach, and has two sets of parallel memory, you can realize continuous data stream operations, will not have data retention and loss
- 2022-01-30 11:03:35下载
- 积分：1
-
xilinx_lib.tar
用于modelsim仿真的xilinxfpga平台IP库，以ise 13.x为基础制作，在modelsim10下验证通过。(xilinx IP core library for modelsim simulate, based on ise 13.x, verified in modelsim10.)
- 2017-10-27 12:23:53下载
- 积分：1
-
exercise3
用verilog实现dsp与Fpga接口的同步设计，其功能包括读写操作及四个功能模块，采用两个fifo实现不同时钟域的地址与数据的转换，在quartus ii11.0环境下运行，运行此程序之前需运行将调用fifo。(Dsp using verilog achieve synchronization with Fpga interface design, its features include read and write operations and four functional modules, using two different clock domains to achieve fifo address and data conversion in quartus ii11.0 environment to run, run this program required before running calls fifo.)
- 2013-08-30 11:12:09下载
- 积分：1
-
QDPSKvhd
说明： 基于quartusII的QDPSK调制解调vhdl程序。(Modulation and demodulation based quartusII of QDPSK vhdl program.)
- 2010-04-23 17:30:53下载
- 积分：1
-
Program to implement convolution through VHDL
Program to implement convolution through VHDL-Program to implement convolution through VHDL...
- 2023-02-08 06:15:02下载
- 积分：1
