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无线发射模块的 SRRC 成型匹配滤波设计 Verilog 代码

于 2022-11-23 发布 文件大小:11.60 kB
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无线发射模块的 SRRC 成型匹配滤波设计 Verilog 代码,包含了所有测试,主模块,可以用在基带调制端,滤波器的滚降系数0.10~0.25,如果那些没有做过这方面的朋友,可以看看实现,和方法,提供一个参考和帮助

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