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VHDL_Led control single light from right to left( điều khiển led sáng dồn từ phải sang trái)
- 2023-08-04 23:15:03下载
- 积分:1
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用于fpga学习,共同分享学习经验和交流学习心得
用于fpga学习,共同分享学习经验和交流学习心得-For fpga to learn, to share learning experiences and the exchange of learning
- 2022-02-25 22:21:38下载
- 积分:1
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Turbo码编码译码器的研究及其FPGA实现.
在Altera公司的Quartus
II软件平台下完成了基于Log-MAP算法的Turbo码编译码器的FPGA设计及实现。在Turbo码的FPGA设计与实现部分,主要针对了
Turbo码的编译码器中各个重要模块进行了设计和实现,例如编码器中RSC分量译码器、交织器,以及译码器中对数据量化和运算、E函数、SISO分量译码器(分支度量、前向递推、后向递推以及对数释然比的计算)的设计与实现。
- 2022-08-25 16:51:06下载
- 积分:1
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fft64
verilog hdl 编写的64点fft代码,适合很多芯片(coded by verilog hdl that implement 64 point fft, suite to many core)
- 2020-12-12 21:19:16下载
- 积分:1
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vhdl um teste com muita coisa interessante ae pra ver
vhdl um teste com muita coisa interessante ae pra ver
- 2023-07-05 20:40:02下载
- 积分:1
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bishe
基于FPGA 的VGA波形显示,dds产生三角波正弦波(Vga waveform display based on FPGA, using DDS to generate sinusoidal triangular wave)
- 2018-12-12 11:26:37下载
- 积分:1
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huawei
华为内部资料,包括verilog电路设计,硬件工程师手册,verilog约束,synplify使用指南等。内容较全面。(Huawei internal information, including verilog circuit design, hardware engineers manual, verilog constraints, synplify use guides. Content more comprehensive.)
- 2015-07-11 20:08:52下载
- 积分:1
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CODE_VHDL_COUNTING 0 到 9 (慈 0 đến 9 Đếm hiển đoạn 施耐 1 带领 7)
CODE_VHDL_COUNTING 0 到 9 (慈 0 đến 9 Đếm hiển đoạn 施耐 1 带领 7)
- 2023-04-13 10:55:04下载
- 积分:1
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paidui
排队电路设计,适用于EDA大作业,大学生适合使用,初学者,仅仅是vhdl的语言,可以借鉴(Queuing circuit design, suitable for EDA operation, college students suitable for use, beginners, only the language of VHDL, can learn from)
- 2017-12-10 23:47:23下载
- 积分:1
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uart_tx
FPGA UART 发送端程序 verilog语言编写
9600波特率 实用(UART transmit side program verilog language 9600 baud)
- 2013-08-14 16:33:34下载
- 积分:1