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本文档是 Java 2 Platform Standard Edition 6.0 的 API 规范。
本文档是 Java 2 Platform Standard Edition 6.0 的 API 规范。-This document is a Java 2 Platform Standard Edition 6.0 of the API specification.
- 2023-07-24 14:40:10下载
- 积分：1
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VFP6.0中应用activeskin换肤控件源码
VFP6.0中应用activeskin换肤控件源码-VFP6.0 Application Control source activeskin Eurocargo
- 2022-03-23 17:23:49下载
- 积分：1
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LM1117 Chinese descriptive information on the power supply system were developed...
LM1117的中文说明资料，共开发供电系统的朋友查阅-LM1117 Chinese descriptive information on the power supply system were developed friend Search
- 2023-05-07 12:00:03下载
- 积分：1
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C语言编程常用技巧
C语言编程常用技巧-C programming language commonly used techniques
- 2022-04-16 10:07:19下载
- 积分：1
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more free source of the hooligan source hut : http :// 488073.tomore.com /
更多免费源码在阿飞源码小屋：http://488073.tomore.com/-more free source of the hooligan source hut : http :// 488073.tomore.com /
- 2022-01-22 04:51:50下载
- 积分：1
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经典tcp文章，阐述算法原理及其应用。而且是英文版本
经典tcp文章，阐述算法原理及其应用。而且是英文版本-classic tcp article described algorithm theory and its application. Is the English version
- 2022-01-26 00:00:18下载
- 积分：1
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Introduce how to program for linux
Introduce how to program for linux
- 2023-05-03 23:50:04下载
- 积分：1
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发展微软ASP.NET服务器控件和组件
Developing Microsoft ASP.NET Server Controls and Components
- 2023-01-20 00:05:04下载
- 积分：1
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FPGA pipelined designs on paper This work investigates the use of very deep pipe...
关于FPGA流水线设计的论文
This work investigates the use of very deep pipelines for
implementing circuits in FPGAs, where each pipeline
stage is limited to a single FPGA logic element (LE). The
architecture and VHDL design of a parameterized integer
array multiplier is presented and also an IEEE 754
compliant 32-bit floating-point multiplier. We show how to
write VHDL cells that implement such approach, and how
the array multiplier architecture was adapted. Synthesis
and simulation were performed for Altera Apex20KE
devices, although the VHDL code should be portable to
other devices. For this family, a 16 bit integer multiplier
achieves a frequency of 266MHz, while the floating point
unit reaches 235MHz, performing 235 MFLOPS in an
FPGA. Additional cells are inserted to synchronize data,
what imposes significant area penalties. This and other
considerations to apply the technique in real designs are
also addressed.-FPGA pipelined designs on paper This work invest
- 2022-11-28 12:05:03下载
- 积分：1
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ELF 文件格式详解，为想学习动态加载技术的基础教材
ELF 文件格式详解，为想学习动态加载技术的基础教材-Detailed ELF file format
- 2022-06-12 13:35:26下载
- 积分：1
