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testbench.sv
RS 编码和解码Verilog Code, 实现了RS（544,514)的编码和译码；(-RS Coding and Decoding Verilog code， implement RS（544,514))
- 2016-09-25 16:05:54下载
- 积分：1
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dac_spi
DA9125 配置spi程序 正弦波产生(DA9125 configuration spi program sine wave generated)
- 2017-05-27 20:17:40下载
- 积分：1
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can-lite-vhdl-master
CAN VHDL Code. Behavioral implementation of CAN bus interface.
- 2021-01-19 21:48:41下载
- 积分：1
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用状态机实现一序列检测器，即检测到串行码{1110010}后，检测器输出1，否则输出0；...
用状态机实现一序列检测器，即检测到串行码{1110010}后，检测器输出1，否则输出0；
-State machine used to achieve one sequence detector, which detects the serial code (1110010), the detector output 1, otherwise output 0
- 2022-02-05 19:06:27下载
- 积分：1
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FPGA按键加蜂鸣器实验
FPGA按键加蜂鸣器实验：
加延时防抖+蜂鸣器(Experiments of keys and buzzers in FPGA)
- 2020-06-22 04:00:01下载
- 积分：1
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Static RAM is a tube composed of MOS flip
静态RAM是由MOS管组成的触发器电路，每个触发器可以存放1位信息。只要不掉电，所储存的信息就不会丢失。因此，静态RAM工作稳定，不要外加刷新新电路，使用方便。但一般SRAM的每一个触发器是由6个晶体管组成，SRAM芯片的集成度不会太高，目前较常用的有6116（2K×8位），6264（8K×8位）和62256（32K×8位）。6264RAM有8192个存储单元，每个单元为8位字长。-Static RAM is a tube composed of MOS flip-flop circuit, each flip-flop can store one message. Long as it does not brown-out, the stored information will not be lost. Therefore, the static stability in the work RAM, do not refresh plus the new circuit and easy to use. But generally each SRAM trigger is composed of six transistors, SRAM chip integration will not be too high, there are currently more commonly used 6116 (2K × 8 bit), 6264 (8K × 8 bit) and 62256 (32K × 8 bits). 6264RAM have 8192 storage units, each for 8-bit word length.
- 2022-04-10 07:00:36下载
- 积分：1
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利用FPGA采集按键，加了消斗。其实跟单片机的效果差不多。
利用FPGA采集按键，加了消斗。其实跟单片机的效果差不多。-The use of FPGA collect keys, plus the elimination fighting. In fact, almost with the effect of SCM.
- 2023-03-12 23:10:03下载
- 积分：1
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VHDL
软件式的VHDL学习工具，能帮助你更好的掌握VHDL的应用-VHDL-based software, learning tools, can help you better grasp the application of VHDL
- 2022-07-01 16:13:22下载
- 积分：1
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VHDL语言，设计一个在DE2平台的8个七段数码管上循环显示HELLO的程序
VHDL语言，设计一个在DE2平台的8个七段数码管上循环显示HELL0的程序，采用按键控制循环的速度，慢速循环时间间隔为1S，快速循环时间间隔为200ms。(VHDL language, design a platform in the DE2 8 segment digital tube display HELL0 program cycle, the speed control loop using keys, slow cycle time interval for the 1S, fast cycle time interval is 200ms.)
- 2020-07-08 20:28:56下载
- 积分：1
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dcfifo_design_example
ALTERA发布的内部FIFO读写示例，很有参考价值，对初学者会有一定的帮助(ALTERA' s internal FIFO read and write examples of great reference value, there will be some help for beginners)
- 2010-11-13 23:31:11下载
- 积分：1
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