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ALU_verilog
用verilog语言编写的4位算术逻辑单元ALU,功能参考74181,包含.v文件以及测试用.vwf文件(Verilog languages with four arithmetic logic unit ALU, functional reference to 74,181, including. V documents and testing. Vwf document)
- 2008-08-15 11:36:51下载
- 积分:1
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Verilog实现的VGA程序,用ISE打开工程文件即可
Verilog实现的VGA程序,用ISE打开工程文件即可-Verilog implementation VGA program, open the project file with the ISE can be
- 2022-03-11 09:21:27下载
- 积分:1
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matlab
matlab file for image contrast..
- 2010-08-18 03:02:21下载
- 积分:1
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32位ALU
这个我弄了好久,伤心了。不过,自己喜欢,终于把他给做了出来,过程是相当的复杂,不信。你们可以下下来看看,有不懂得可以咨询我
- 2022-03-04 00:04:32下载
- 积分:1
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USB 1.1 PHY code systemc language USB 1.1 PHY code, systemc languages, including...
USB 1.1 PHY的代码,systemc语言 USB 1.1 PHY的代码,systemc语言,包括基于systemc语言的testbench ,和相关的doc文档-USB 1.1 PHY code systemc language USB 1.1 PHY code, systemc languages, including systemc based testbench language, doc and related documents
- 2022-04-12 00:51:05下载
- 积分:1
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RS232_VHDL
FPGA控制RS232来实现串口通信,非常好的串口程序。(FPGA control RS232 serial communication to achieve very good serial procedures.)
- 2020-12-28 14:49:01下载
- 积分:1
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三体模型
三体模型仿真计算样例,基于特定的java浏览器插件对象,以非常形象的方式展示了三体运动物体的规律,可以调节运动参数,实时查看运动变化情况。
- 2022-05-23 17:18:16下载
- 积分:1
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UBlaster
USB Blaster full production data
- 2011-06-17 16:03:28下载
- 积分:1
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ran_num_generator.tar
vhdl random numbergenerater
- 2013-04-10 16:31:28下载
- 积分:1
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5-15
用verilog语言实现基于DDS技术的余弦信号发生器,其输出位宽为16比特(Verilog language cosine signal generator based on DDS technology, the output bit width is 16 bits)
- 2013-04-18 22:58:05下载
- 积分:1