-
VHDL language used to achieve a display hours, minutes and seconds of the clock:...
用VHDL语言实现一个能显示时、分、秒的时钟：可分别进行时和分的手动校正；12小时、24小时计时制可选，12小时制时有上下午指示；当计时到预定时间（此时间可手动设置）时，扬声器发出闹铃信号，闹铃时间为10秒，可提前终止闹铃。-VHDL language used to achieve a display hours, minutes and seconds of the clock: when can be manually corrected and points 12 hours, optional 24-hour time system, 12-hour on the afternoon of instructions from time to time when the time to the scheduled time (This time can be manually set), the speaker sent alarm signals, alarm time was 10 seconds, the alarm can be terminated prematurely.
- 2022-04-27 22:51:31下载
- 积分：1
-
stm8uart
Demo program for use UART STM8S
- 2013-09-05 03:18:35下载
- 积分：1
-
or2a
使用vhdl语言设计一位全加器，在仪器上下载并实现LED灯的闪亮(A full adder design)
- 2013-09-26 18:24:15下载
- 积分：1
-
Verilog_Basic
说明： Verilog 入门,如果你要很了解Verilog你不用先谖完一本厚厚的书还弄不清楚Verilog到底在干啥事,这份资料有助於快速了斛Verilog(Verilog Basic, If you try very hard to understand verilog by read a thick book, try read this first you will get a quick understanding of verlog.)
- 2010-03-19 09:02:22下载
- 积分：1
-
FIFO
FIFO的源代码，对FIFO设计有帮助，有借鉴意义，帮助学习VHDL编程(FIFO of the source code, on the FIFO design help, there is reference to help learn VHDL programming)
- 2008-04-29 09:00:11下载
- 积分：1
-
vhdl应用汇编所写的关于电梯的详细程序
vhdl应用汇编所写的关于电梯的详细程序-Applications written in VHDL compilation of detailed procedures on the elevator
- 2022-03-18 06:59:58下载
- 积分：1
-
progconterful
four bit counter verlog source code for veriwell including test bench
- 2010-03-29 18:54:45下载
- 积分：1
-
dvb_s2_ldpc_decoder_latest.tar
LDPC COded OFDM System
- 2013-02-09 21:41:33下载
- 积分：1
-
官方的RS232例程详细Altera非常实用
altera 官方rs232例程 很详细很实用-official rs232 routines in great detail altera very practical
- 2023-04-15 09:15:03下载
- 积分：1
-
HDB3modelsim
HDB3编码通过verilog实现，通过modelsim仿真(HDB3 coding is implemented by Verilog and simulated by Modelsim)
- 2020-06-18 05:20:02下载
- 积分：1
