-
用VHDL语言来实现一个电子时钟，可以调时间。小时，分，秒。可以下载到实验箱来运行验证。...
用VHDL语言来实现一个电子时钟，可以调时间。小时，分，秒。可以下载到实验箱来运行验证。-use VHDL to achieve an electronic clock, the time can be set aside. Hours, minutes and seconds. Experiments can be downloaded to the box to run test.
- 2022-07-21 04:12:49下载
- 积分：1
-
本程序为24小时计时器，稳定无误差。简单好用，是Verilog HDL语言初学者的指引。...
本程序为24小时计时器，稳定无误差。简单好用，是Verilog HDL语言初学者的指引。-This procedure for 24-hour timer, stable error-free. Easy-to-use, is the Verilog HDL language beginners guide.
- 2022-07-20 09:46:32下载
- 积分：1
-
READ_SINEX
读取IGS数据中心提供的sinex文件 并恢复法方程(Read sinex file IGS data centers and to restore normal equation)
- 2016-06-18 11:19:14下载
- 积分：1
-
cpri
基于verilog的cpri接口代码，支持各种速率自由切换，量产产品实际应用代码(Cpri interface based on verilog code, support various rate free switch, production products the actual application code)
- 2015-09-21 16:59:59下载
- 积分：1
-
verilog
说明： verilog开发的经典教材，详细介绍了语法，常见历程，以及通用的程序段(verilog development of the classic materials, detailed information on syntax, common history, as well as the common program segment)
- 2010-03-18 12:11:18下载
- 积分：1
-
PWM
自己编写的verilog语言 PWM实现的一种方法希望有用(verilog PWM)
- 2015-04-05 18:23:37下载
- 积分：1
-
ddr2_controller
DDR2控制器设计原码,可以在FPGA上测试通过,并对外部的ddr memory进行读写访问.(DDR2 controller design of the original code, can be tested through the FPGA, and external ddr memory read and write access.)
- 2010-02-23 09:16:50下载
- 积分：1
-
Dual-Mode-Dual-Band-Filters
本文介绍一种波导双模双带滤波器的设计方法。(This paper presents a new class of dual-mode dualband
filters in which each polarization is dedicated to a selected
band. The equivalent circuit is a parallel combination of two inline
networks that represent each polarization. A transmission zero is
generated between the two bands by properly adjusting the relative
orientations of the input and output coupling apertures.)
- 2013-03-12 18:08:33下载
- 积分：1
-
Farrow-filter-design
两篇中文论文，详细叙述了Farrow滤波器的设计方式和理论基础，非常实用！(Two Chinese papers, described in detail Farrow filter design methods and theoretical foundation, very useful!)
- 2013-11-15 17:15:20下载
- 积分：1
-
四VHDL模块的家庭，已经过测试，在ISE8.1通过
四位全家器的VHDL语言模块，已经在ISE8.1上经过测试通过-family of four VHDL modules, has been tested on ISE8.1 through
- 2022-03-21 16:25:17下载
- 积分：1
