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vhdl语言和verilog语言转换工具
能很容易的实现两种语言的相互转换...
vhdl语言和verilog语言转换工具
能很容易的实现两种语言的相互转换-verilog language vhdl language and conversion tools can easily achieve the conversion between two languages
- 2022-08-16 14:34:56下载
- 积分：1
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crc循环冗余校验码，用于对传输信号进行编码校验，是信息更可靠...
crc循环冗余校验码，用于对传输信号进行编码校验，是信息更可靠-crc cyclic redundancy check code used to transmit coded signals to verify, the information is more reliable
- 2022-12-26 06:05:03下载
- 积分：1
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APF_Series_dq0_ad
串联型有源电力滤波器的 PSCAD仿真，能检测到谐波电压，本仿真的优势是能针对电压跌落或者升高进行自动补偿。(PSCAD simulation of Series type APF (Active Power Filter),this project can dectect the drop of voltage and compensates auomaticly.)
- 2013-03-13 22:51:50下载
- 积分：1
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fifo16_16
异步的fifo,写时钟和读时钟相互独立，能够对数据进行缓存处理。希望对大家有用(Asynchronous fifo, write clock and the read clock independent of each other, capable of processing the data cache. I hope useful)
- 2020-10-26 10:49:59下载
- 积分：1
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由avalen总线转接i2c总线的vhdl程序 可应用于nios嵌入式系统
由avalen总线转接i2c总线的vhdl程序 可应用于nios嵌入式系统-By avalen bus adapter i2c bus VHDL program can be applied to Nios Embedded Systems
- 2022-02-28 11:19:17下载
- 积分：1
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PRBS
代码是伪随机数生成和检测的模块，用于通信行业的FPGA编程。包括VHDL和Verilog两种语言的版本。用于做接口测试。(This module generates or check a PRBS pattern.)
- 2021-05-08 11:58:35下载
- 积分：1
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Protel_book
protel经典教程，并附有一张电路设计原理图(protel classic tutorials, together with a circuit design schematic)
- 2010-05-28 17:06:44下载
- 积分：1
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MB
说明： 基于VHDL语言数字秒表设计,在FPGA实验平台下开发(Digital stopwatch design based on VHDL, FPGA experimental platform under development)
- 2015-04-21 20:11:14下载
- 积分：1
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vendingmachine
vendingmachine vhdl code
- 2011-12-03 20:53:39下载
- 积分：1
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本实施multilplier在vhdl.this源代码是有用的电脑学习…
this implemented multilplier in vhdl.this source code is useful for computer student and hardware engineering.-this is implemented multilplier in vhdl.this source code is useful for computer student and hardware engineering.
- 2022-01-31 00:27:28下载
- 积分：1
