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scan_led
FPGA扫描LED显示灯，动态扫描,进行流水显示(FPGA Scan LED indicator lights, dynamic scanning, make the water show)
- 2015-02-16 18:02:16下载
- 积分：1
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breathingLED
stc12c5a60s2单片机做的两路呼吸灯，可以用ad和按键控制闪动频率(stc12c5a60s2 SCM done with the two breathing lights, you can use the ad and buttons to control the flashing frequency)
- 2013-05-10 15:33:18下载
- 积分：1
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pipeline_FPGA
FPGA流水线设计的资料，可以作为学习FPGA开发并行操作的一个经典教材，具有很好的指导作用。(FPGA pipeline design information can be developed as a learning FPGA parallel operation of a classic textbook, has a good guide.)
- 2011-07-02 12:00:57下载
- 积分：1
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VHDL_freerisc8
说明： 一个8位RiSC单片机的VHDL代码，
具有很好的参考价值。(an eight RiSC SCM VHDL code, is a good reference value.)
- 2006-02-15 10:58:14下载
- 积分：1
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fft64
verilog hdl 编写的64点fft代码，适合很多芯片(coded by verilog hdl that implement 64 point fft, suite to many core)
- 2020-12-12 21:19:16下载
- 积分：1
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filter
说明： A low pass filter module based on FPGA, easy to transplant
- 2020-05-04 10:21:42下载
- 积分：1
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Single-CPU
简单的单周期CPU设计，实现的指令有：算术运算指令、逻辑运算指令、移位指令、比较指令、存储器读/写指令、分支指令、跳转指令、停机指令。(Simple single-cycle CPU design,The instructions implemented are as follows:Arithmetic operation instruction, logical operation instruction, shift instruction, comparison instruction, memory read/write instruction, branch instruction, jump instruction, stop instruction.)
- 2020-06-16 12:28:32下载
- 积分：1
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a2
说明： 用MATLAB设计及FPGA实现IIR滤波器的方法
摘要 本文介绍了IIR数字滤波器的传统设计思想与步骤及计算机辅助设计方法。并在FPGA上高效实现的低阶IIR滤波
器，其阶数低，实时响应快，适合雷达等的实时、高效处理环境。利用IIR滤波器的多相结构来实现该滤波器系统的方法，对于
四通道的情形在MATLAB上利用Simulink作了仿真, 并在目标板上对算法进行了实现,证明该系统能够同时处理四个通道的信号。(Using MATLAB Design and FPGA realization IIR Filter method Abstract This paper introduces IIR digital filter traditional design Thought and steps and CAD method. And FPGA on efficient realization low IIR filter, its order low, real response fast suitable radar real time, efficient processing environment. Use IIR filter multiphase structure realize the filter systematic method, for four channel circumstances in MATLAB on use Simulink made simulation and target board algorithm was realized proved system can simultaneously four channel signal.)
- 2010-04-01 17:10:21下载
- 积分：1
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VHDL产生时钟50分频程序，供初学者参考
VHDL产生时钟50分频程序，供初学者参考-VHDL generated clock frequency of 50 procedures, the reference for beginners
- 2022-03-06 08:34:20下载
- 积分：1
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DongHo
design a clock using KIT DE1
- 2014-09-19 04:46:23下载
- 积分：1
