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用NiosII实现的数字钟，经过本人测试运行正常，开发环境：QuartusII6.0和NiosII IDE6.0...
用NiosII实现的数字钟，经过本人测试运行正常，开发环境：QuartusII6.0和NiosII IDE6.0-NiosII achieved with digital clock, after I run the normal tests, development environment: QuartusII6.0 and NiosII IDE6.0
- 2023-04-12 03:05:04下载
- 积分：1
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ComunicationRealizationBetweenFPGAandSerialInterfa
说明： 杜晓斌和陈兴文-FPGA和单片机串行通信接口的实现一文提出了FPGA与单片机实现数据串行通信的解决方案。在通信过程中完全遵守RS232 协议，给出了发送模块的vhdl源代码。
(杜晓斌and陈兴文-FPGA single-chip serial communication interface and the realization of a text proposed by the FPGA and MCU serial data communications solutions. In the communication process in full compliance with the RS232 protocol is given to send the VHDL source code modules.)
- 2008-11-18 15:41:34下载
- 积分：1
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password
verilog代码实现的数字密码锁。通过4个并行的10位移位寄存器，分别记录在时钟上升沿时A,B,C,D的输入情况，比如某上升沿输入A，相应时刻A对应的移位寄存器输入1，其他三个移位寄存器输入都为0.另外4个并行的10位寄存器记录密码。这样，密码锁不仅可以识别字符数量，还可以判断出字符的输入次序。(verilog code of digital lock. By four parallel 10-bit shift register, respectively, recorded in the clock rising edge A, B, C, D of inputs, such as a rising edge of input A, the corresponding moments A 1 corresponding to the input shift register, the other three shift bit register inputs are 0. another four parallel 10-bit registers record the password. This lock can not only identify the number of characters, you can also determine the character of the input sequence.)
- 2011-10-18 21:45:45下载
- 积分：1
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verilog_DATA_displays
使用verilog语言，滚动显示“verilog”字符串程序代码及相关说明(Using verilog language, scrolling display " verilog" string code and instructions)
- 2014-01-16 10:49:55下载
- 积分：1
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利用vhdl编写的双端口Ram程序，不带数据纠错处理
利用vhdl编写的双端口Ram程序，不带数据纠错处理-VHDL prepared to use dual-port Ram procedures, do not deal with data error correction
- 2023-03-13 05:20:04下载
- 积分：1
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bayer_3RGB_interpolation
一个基于FPGA用verilogHDL设计的bayer格式转RGB格式的模块，本人设计(a code used for bayer_3RGB_interpolation ,which based on FPGA by verilogHDL)
- 2011-12-25 21:58:05下载
- 积分：1
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which I have recently bought a CPLD Development Board VHDL source code accompani...
这是我最近买的一套CPLD开发板VHDL源程序并附上开发板的原理图,希望对你是一个很好的帮助!其中内容为:8位优先编码器,乘法器,多路选择器,二进制转BCD码,加法器,减法器,简单状态机,四位比较器,7段数码管,i2c总线,lcd液晶显示,拨码开关,串口,蜂鸣器,矩阵键盘,跑马灯,交通灯,数字时钟.-which I have recently bought a CPLD Development Board VHDL source code accompanied the development of the plate diagram, You hope to be a good help! which states : eight priority encoder, multipliers, multi-path selectors, BCD binary switch, adder, subtraction device, the simple state machine, four comparators, seven of the digital control, i2c bus, lcd LCD allocated code switches, serial port, the buzzer sounded, matrix keyboards, Bomadeng, traffic lights, Digital Clock.
- 2022-02-20 05:51:18下载
- 积分：1
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This is is a bridge IP core to interface the Tensilica PIF bus protocol with the...
This is a bridge IP core to interface the Tensilica PIF bus protocol with the OpenCores WishBone. It currently supports single-cycle as well as burst transfer operations. The core has been tested in a master-PIF slave-WB configuration.-This is is a bridge IP core to interface the Tensilica PIF bus protocol with the OpenCores WishBone. It currently supports single-cycle as well as burst transfer operations. The core has been tested in a master-PIF slave-WB configuration.
- 2022-04-07 07:47:24下载
- 积分：1
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蓝牙HCI―UART与并口的FPGA控制接口设计
蓝牙HCI―UART与并口的FPGA控制接口设计-Bluetooth HCI-UART and parallel port control interface of the FPGA design
- 2022-07-10 22:33:51下载
- 积分：1
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用VHDL写的运动计时表程序，用Modelsim仿真已经通过，帖出来与大家分享。...
用VHDL写的运动计时表程序，用Modelsim仿真已经通过，帖出来与大家分享。-write VHDL campaign time table program, Modelsim simulation has been passed, Tie up share with you.
- 2022-01-26 05:57:13下载
- 积分：1
