-
lab6-3-8DECODER
数字设计和计算机体系结构：用verilog语言描述3-8译码器的设计与实现(Digital design and computer architecture: use verilog language describe 3-8 decoder design and implementation)
- 2016-10-24 17:20:07下载
- 积分：1
-
DDC_Ver1.0
数字下变频（DDC）在如今基于软件无线电的架构中对系统的整体性能决定性的影响，代码为基于Matlab的4通道DDC程序，程序中可以根据需要调节滤波器等参数评估DDC的性能对于使用FPGA实现DDC有较大的参考价值(Digital down conversion (DDC) in today' s architecture based on software radio system a decisive impact on the overall performance of the code for the 4-channel DDC Matlab-based program, the program can be adjusted according to filter parameters such as the use of performance assessment FPGA DDC DDC has achieved great reference value)
- 2010-08-04 18:33:14下载
- 积分：1
-
按键在数字电路设计中经常用到。按键的弹跳现象是数字系统设计中存在的客观问题。按键是机械触点，当接触点断开或闭合时会产生抖动。为使每一次按键只做一次响应，就必须去...
按键在数字电路设计中经常用到。按键的弹跳现象是数字系统设计中存在的客观问题。按键是机械触点，当接触点断开或闭合时会产生抖动。为使每一次按键只做一次响应，就必须去除抖动。本文对按键的抖动信号进行了分析，并通过计数器的方式完成了消除抖动电路模块的设计-?
- 2022-08-07 18:25:32下载
- 积分：1
-
数字频率计 FPGA 用verilog语言编写
数字频率计 FPGA 用verilog语言编写-Digital Cymometer verilog language used FPGA
- 2023-01-25 21:10:03下载
- 积分：1
-
很不容易找到的资料，基于VHDL的频率计设计 希望有用
很不容易找到的资料，基于VHDL的频率计设计 希望有用-Not easy to find information on the frequency meter based on the VHDL design seek to help
- 2022-04-21 13:02:06下载
- 积分：1
-
multi8x8
节约资源型 8位*8位 运算VHDL代码，采用串行运算，8 个时钟周期完成一次运算。QUARTUS下已验证(resource conservation-8* 8 Operational VHDL code, using serial computation. 8 clock cycles to complete an operation. QUARTUS has been under test)
- 2006-12-07 13:22:48下载
- 积分：1
-
FIR_poroje
this project is about FIR FIlter By VHdl codes in the ISE.
- 2013-09-29 19:25:16下载
- 积分：1
-
YCbCr444_YCbCr422
FPGA YCbCr444转YCbCr422实验 很好的参考(FPGA EP4CE40F23C6 YCbCr444 turn YCbCr422 experiment)
- 2021-01-25 10:08:38下载
- 积分：1
-
DDS
文利用直接数字频率合成器(DDS)与CPLD技术和单片机控制技术，研制和
设计了高分辨率、高稳定度的函数信号发生(Wen using direct digital frequency synthesizer (DDS) and CPLD technology and single-chip microcomputer control technology, development and
Design of high resolution, high stability function of the signal
)
- 2013-08-27 14:20:22下载
- 积分：1
-
usbd_ucos
说明： 基于ALINX AX7020硬件平台的USB-OTG通信程序。操作系统采用uCOS III v1.41，基本实现了双向USB2.0 块传输（Bulk Transfer）通信，zynq的PS端接收USB数据并回传至主机。经测试，主机端Window10系统采用libUSBK编程时，采用64字节的块时，传输速率可达210Mbps。zynq开发工具为Vivado2015.4，程序包中包含了全部的硬件和软件工程文档。(A USB-OTG communication project where an AX7020 platform is employed as USB device. The embeded operating system is uCOS III of version 1.41, and the FPGA toolchain is Vivado 2015.4. This project implements a full speed bidirectional USB2.0 bulk transfer. A test on Windows 10 host with libUSBK shows that the transfer speed is up to 201Mbps.)
- 2020-09-09 09:38:02下载
- 积分：1
