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add1A
用于实现锁相光子计数技术的累加器，verilog语言(Accumulator achieve specific cases for accumulator lock detection of photon counting technique)
- 2016-04-09 11:13:25下载
- 积分：1
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UART_Test
OMAP5912 UART的测试程序 包括头文件 源文件等。(OMAP5912 UART program test)
- 2011-08-14 16:04:03下载
- 积分：1
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IEEE_030_powerworld
The IEEE 30-bus modified test system has 6 synchronous machines with IEEE type-1 exciters, 4 of which are synchronous compensators, 36 buses, 37 transmission lines, 10 transformers and 21 constant impedance loads. The total load demand is 283.4 MW and 126.2 MVAr.
- 2020-07-03 02:20:02下载
- 积分：1
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RS_Encode_Decode
RS(255,223)编解码算法。verilogHDL代码实现，在XILINX的芯片上得到验证。不包含任何IP核，方便移植到任何FPGA芯片。(RS (255223) encoding and decoding algorithm. VerilogHDL code to achieve, in the XILINX chip to be verified. Does not contain any IP core, easy to transplant to any FPGA chip.)
- 2016-01-21 12:07:34下载
- 积分：1
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RS232协议的fpga实现
RS232协议的fpga实现，工业应用中可以灵活的应用ps2协议设备，并且可以快速修改，本协议是采用verilog实现的。
- 2022-07-25 23:39:57下载
- 积分：1
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RobustVerilog_free1.2_win
RobustVerilog生成verilog工具(RobustVerilog version)
- 2021-01-22 18:18:41下载
- 积分：1
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Verilog
Verilog经典教程，很好的学习Verilog的书籍，对学习硬件编程很有帮助。(Verilog classic handbook, good learning Verilog books, to learn hardware programming helpful.)
- 2013-08-19 11:02:51下载
- 积分：1
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RSA的VHDL代码
Here, we present the first available open-source 512 bit RSA core. This is an early
prototype version of a full FIPS Certified 512-4096 capable RSA Crypto-core which will be on sale
soon. The version provided, has not the same performance than the final product since it was a
proof of concept that we decided to release to the community in order to help small projects which
need RSA ciphering.
- 2022-09-07 05:20:03下载
- 积分：1
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AXI slave
一个AXI slave的Verilog实现代码，内部有基于UVM编写的testbench,该slave是基于AXI3协议来实现的，可以给初学者一些启示
- 2023-09-07 19:50:05下载
- 积分：1
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scramble
基于VHDL实现加扰器解扰器的设计，与仿真。(VHDL-based scrambler descrambler design and simulation.)
- 2013-01-11 20:15:54下载
- 积分：1
