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apb_spi
Simple SPI interface realization on Verilog HDL with parameterized FIFO and APB interface
- 2021-04-06 16:19:02下载
- 积分：1
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asynchronous reset state machine
异步复位状态机
-- State Machine with Asynchronous Reset
-- dowload from: www.fpga.com.cn & www.pld.com.cn
-asynchronous reset state machine-- State Machine with Asynchronou "s Reset-- dowload from : www.fpga.com.cn
- 2023-07-14 12:30:03下载
- 积分：1
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It is a fir to implement in a FPGA. It s not desenvolved for me it is a good wor...
It is a fir to implement in a FPGA. It s not desenvolved for me it is a good work of another person
- 2022-03-29 20:48:40下载
- 积分：1
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updown
VHDL Programmes -2 for dumping on FPGA
- 2014-02-12 00:22:46下载
- 积分：1
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用数码管显示时间的数字电子钟verilog编写
用VERILOG编写的数字电子钟，用数码管进行显示时间-VERILOG prepared with digital electronic clock with a nixie tube display time
- 2022-06-22 05:51:35下载
- 积分：1
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demo_as32ttl1w
可以获取各种字符，并在数码管显示出来，非常的靠谱且稳定(Various characters can be acquired and displayed on the digital tube.)
- 2020-06-16 15:00:02下载
- 积分：1
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基于DE2开发板，视频图像显示设计源代码，代码调试成功
基于DE2开发板，视频图像显示设计源代码，代码调试成功-based DE2 development board ,it is vhdl resourse code
- 2022-03-15 06:09:25下载
- 积分：1
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坦克游戏的VHDL代码
坦克游戏用VHDL语言编写。Altera的随身携带套件DE1。PS2键盘接口和VGA
- 2022-03-14 20:16:04下载
- 积分：1
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Coding Style
良好的Coding Style能减少Bug，减少锁存器出现的可能以及其他隐藏逻辑错误，也有助于减小芯片面积或所用资源(Good Coding Style can reduce Bug, reduce the possibility of latches and other hidden logic errors, and also help to reduce chip area or resources used.)
- 2020-06-17 12:00:01下载
- 积分：1
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Asynchronous FIFO controller Verilog Design and Implementation
异步FIFO控制器的Verilog设计与实现-Asynchronous FIFO controller Verilog Design and Implementation
- 2022-08-14 15:39:50下载
- 积分：1
