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lsd
按键控制LED流水灯；按键1按下前8个灯从左到右依次点亮，按键2按下中间前8个灯从左到右依次点亮，按键3按下所有灯全亮(Water control button LED lights sequentially lit buttons the eight lights left to right 1 Press button 2 press from left to right is lit in the middle eight lights, key 3 Press All full bright light)
- 2012-10-17 18:23:36下载
- 积分：1
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Xilinx PCIcore have a detailed description of official documents, to support the...
锡林克斯巴达官方文件有详细说明，支持斯巴达、顶点
- 2022-02-27 03:33:26下载
- 积分：1
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dp_xiliux the CPLD Verilog design experiments, clock demo. code test.
dp_xiliux 的 CPLD Verilog设计实验,时钟演示.代码测试通过. -dp_xiliux the CPLD Verilog design experiments, clock demo. code test.
- 2022-12-25 17:55:03下载
- 积分：1
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1.rar
此为数字逻辑书上的答案，应该很多同学都需要吧，关于数字逻辑(This is the answer books, digital logic, it should be a lot of students need it, on the digital logic)
- 2009-09-17 13:16:19下载
- 积分：1
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基于FPGA的彩色符号设计
a、设计可显示横彩条和纵彩条的VGA彩条信号；
b、设计可显示英语字母的VGA彩条信号；
c、设计可显示移动彩色斑点的VGA彩条信号；
d、设计可实现手动切换a、b、c三个功能.(The design can display VGA color color and color of the longitudinal cross signal.
The design can display the VGA color signal of the English alphabet.
The design can display the VGA color signal of mobile color spots.)
- 2020-11-09 16:29:46下载
- 积分：1
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State machine used to achieve code lock
用状态机实现密码锁State machine used to achieve code lock-State machine used to achieve code lock
- 2022-10-12 19:25:03下载
- 积分：1
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build a tv box on fpga cyclone 2
build a tv box on fpga cyclone 2
- 2022-03-10 23:00:00下载
- 积分：1
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黄金时段介绍STA
PrimeTime Intro to STA
-PrimeTime Intro to STA
- 2022-12-10 13:05:05下载
- 积分：1
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这是用Verilog HDL写的可调占空比分频控制器，可以挂在Avalon总线上使用...
这是用Verilog HDL写的可调占空比分频控制器，可以挂在Avalon总线上使用-This is written in Verilog HDL with adjustable duty cycle frequency controller, can be hung on the Avalon bus use
- 2022-09-09 08:45:02下载
- 积分：1
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I2C_ise9migration
说明： IIC 的Verilog实现，工程是在Xilinx的ISE9.1上实现的(IIC of the Verilog implementation project was implemented on Xilinx' s ISE9.1)
- 2010-04-02 09:26:54下载
- 积分：1
