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huffman
huffman transform in vhdl language
- 2013-08-26 13:17:15下载
- 积分：1
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Min-Max
calculate min max of series of nb
- 2009-08-08 16:26:52下载
- 积分：1
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vga接口的工程实现，基于altera环境，需要的可以
vga接口的工程实现，基于altera环境，需要的可以-vga interface engineering implementation, based on altera environment, need to take a look at
- 2023-04-22 21:05:04下载
- 积分：1
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the booth algorithm to implement the 32bit 's multiplication.
the booth algorithm to implement the 32bits multiplication.-the booth algorithm to implement the 32bit "s multiplication.
- 2022-10-16 05:40:03下载
- 积分：1
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qiangdaqi
本程序为四路抢答器verlog HDL语言工程实例。(This program is four Responder verlog HDL language engineering examples.)
- 2013-10-30 14:48:21下载
- 积分：1
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54948739-Digital-Signal-Processing-With-Field-Pro
I am in need of some codes of HDL
- 2014-02-10 22:18:48下载
- 积分：1
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在QuartusII运用ＡＨＤＬ语言，首先设计出PN发生器来产生一个11位的数据流在整个周期内有效数据有 =2047位；再设计状态机用来检测串行数据流中的序列。...
在QuartusII运用ＡＨＤＬ语言，首先设计出PN发生器来产生一个11位的数据流在整个周期内有效数据有 =2047位；再设计状态机用来检测串行数据流中的序列。运用两个个计数器分别对PN码计数以及序列出现的次数计数。改变ＰＮ码结构可以作为通用数列检测器-QuartusII use in AHDL language, the first PN generator designed to generate a data stream 11 throughout the cycle has an effective data = 2047 re-designing the state machine used to detect the serial data stream in sequence. The use of two counters were counting on the PN code, as well as counting the number of sequences occur. Changes in the structure of PN code series can be used as general-purpose detector
- 2023-03-11 09:20:03下载
- 积分：1
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clock
本程序实现数字钟系统，有整点报时功能，可显示切换年月日，定时功能(Digital clock system of this program, with the whole point timekeeping function, can display the date, the timing function)
- 2015-04-19 22:07:02下载
- 积分：1
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bldc_motor_control_design_example
无刷直流电机 VHDL VERILOG 控制,速度环，RS232 串口接收发送 始终分频 PWM生成 电机相序 actel FPGA使用-VERILOG BLDC control of the use of actel FPGA( actel VERILOG BLDC control of the use of actel FPGA)
- 2020-10-29 09:19:57下载
- 积分：1
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用于当前电子的开关电源转换器（开关电源）。
开关电源变换器（Switching Power Supply）为当前电子产品中应用非常广泛的功率器件，在日常生活中无处不在
- 2022-10-24 21:50:03下载
- 积分：1
