-
aFifo
verylog语言编程，为异步flipflop的程序。具有数据传输功能，数据位数可以用户设定(verylog language programming for asynchronous Flipflop procedures. With a data transmission function, data can be user set the median)
- 2007-08-28 10:26:03下载
- 积分：1
-
BRAT
early branch rename table(store rename table once the branch instruction comes in. Used in out of order pipeline processor)
- 2012-03-27 15:15:08下载
- 积分：1
-
ser_to_parr
很有用的10bit串并转换verilog程序，需要的可以拿去参考下，在quartusII上已验证过(Useful 10bit string and convert verilog program, need to take a reference, has been verified in quartusII)
- 2012-05-21 16:21:22下载
- 积分：1
-
ram_test
说明： 对片内RAM进行读写操作，通过数据的写入和读出，对RAM的操作进行熟悉。(Read and write ram on chip, and get familiar with RAM operation through data writing and reading.)
- 2020-08-17 11:38:22下载
- 积分：1
-
FIR_filter
说明： 滤波器就是对特定的频率或者特定频率以外的频率进行消除的电路，被广泛用于通信系统和信号处理系统中。(Filter is a circuit that eliminates specific frequencies or frequencies other than specific frequencies. It is widely used in communication systems and signal processing systems.)
- 2020-06-21 14:00:01下载
- 积分：1
-
DC-Voltmeter
Use this multimeter to make precise electronic measurements and tests. Easy-to-read LCD readout, positive set selector switch and 32" leads. AC voltage
- 2013-01-07 22:52:54下载
- 积分：1
-
TimeQuest就一定要搞定
时序约束方面的经典文章，适合学习FPGA的初学者(A classic article on timing constraints, suitable for beginners to learn FPGA)
- 2018-02-28 11:08:32下载
- 积分：1
-
verilog HDL
说明： DS18B20温度模块，LCD1602显示(DS18B20 Temperature Module, LCD1602 Display)
- 2020-09-04 15:08:06下载
- 积分：1
-
sp6ex7
说明： ISE与Modelsim联合仿真库编译与关联设置。(ISE and Modelsim joint simulation library compilation and associated settings.)
- 2020-07-03 14:17:10下载
- 积分：1
-
rc6_decryption
rc6 algorithm designed based on verilog and is verified
- 2020-12-01 21:59:28下载
- 积分：1
