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TLC5510
TLC5510的驱动程序，采用Verilog语言编写(TLC5510 driver, the use of Verilog language)
- 2020-08-13 21:38:29下载
- 积分：1
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spi_slave
说明： xilinx 平台的SPI从接口实现源码，供参考学习(used xilinx,slave-spi interface.)
- 2019-04-21 12:08:29下载
- 积分：1
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agc_gen
AGC(自动增益放大) Verilog代码 设计可以参考(AGC (automatic gain control) can refer to the Verilog code design
)
- 2015-04-14 01:16:13下载
- 积分：1
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PWM
说明： 通过一个计数器来实现输出信号的占空比要求，可以将duty_cycle分配到拨码开关上,LED分配到发光二极管上,然后调节拨码开关,即可看到LED的亮度发生变化.(The duty cycle of the output signal can be assigned to the dial switch by a counter, and the LED can be assigned to the light emitting diode. Then the brightness of the LED can be seen by adjusting the dial switch.)
- 2020-06-16 13:20:02下载
- 积分：1
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基于FPGA的多功能数字钟的设计与实现 内附有详尽的Verilog HDL源码，其功能主要有：时间设置，时间显示，跑表，分频，日期设置，日期显示等...
基于FPGA的多功能数字钟的设计与实现 内附有详尽的Verilog HDL源码，其功能主要有：时间设置，时间显示，跑表，分频，日期设置，日期显示等-FPGA-based multi-functional Digital Clock Design and Implementation of typhoons and rainstorms are detailed Verilog HDL source code, its functions include: time settings, time display, stopwatch, frequency, date setting, date display
- 2022-02-12 09:36:35下载
- 积分：1
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QPSK_modulation
利用FPGA实现QPSK数字调制。编程采用Verilog HDL语言。(By using the FPGA realization of QPSK digital modulation. Use Verilog HDL language programming.
)
- 2016-03-21 19:53:06下载
- 积分：1
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LEDtest
vhdl 实现fpga 闪灯控制 流水线闪灯 还用signalTAP进行检测，给初学者参考(vhdl fpga flash control lines to achieve flash is also used signalTAP testing, to advanced users)
- 2010-06-10 16:27:57下载
- 积分：1
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FPGA simulation examples, Verilog coding, the process in detail, code easy to un...
FPGA的仿真实例，Verilog代码编写，过程详尽，代码易懂。-FPGA simulation examples, Verilog coding, the process in detail, code easy to understand.
- 2022-07-22 04:45:26下载
- 积分：1
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IRIG_DC_Decoder
IRIG_B解码器，直接解码IRIG_B DC(IRIG_B decoder)
- 2021-04-09 16:58:59下载
- 积分：1
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chuankou
本实验为UART回环实例，实验程序分为顶层unrt_top、发送模块uart_tx、接收模块 uart_rx，以及时钟产生模块clk＿div。uart＿rx将收到的包解析出8位的数据，再传送给 uart_tx发出，形成回环。参考时钟频率为100MHz，波特率设定为9600bps。(This experiment is an example of UART loop. The experimental program is divided into top-level unrt_top, sending module uart_tx, receiving module uart_rx, and clock generation module clk_div. Uart_rx parses the received packet into 8 bits of data and sends it to uart_tx to send out, forming a loop. The reference clock frequency is 100 MHz and the baud rate is set to 9600 bps. stay)
- 2020-06-24 01:40:02下载
- 积分：1
