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VHDL设计：表示和综合（原书第2版）,使用工具dgreader free.exe打开...
VHDL设计：表示和综合（原书第2版）,使用工具dgreader free.exe打开-VHDL Design: express and synthesis (the original version 2), the use of tools to open dgreader free.exe
- 2022-03-02 17:08:03下载
- 积分：1
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c语言的指针应用，一直是大家学习C语言的难点，本书籍专门介绍指针，有PPT演示。方便大家学习...
c语言的指针应用，一直是大家学习C语言的难点，本书籍专门介绍指针，有PPT演示。方便大家学习-c language pointer applications, has been an area difficult to learn C language, this book devoted to the pointer, there are PPT presentation. To facilitate them to learn from
- 2022-02-15 16:53:38下载
- 积分：1
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Borland C Builder Windows API examples
Borland C++ Builder Windows API 实例-Borland C Builder Windows API examples
- 2022-11-25 22:35:03下载
- 积分：1
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vc++经典的仿3D的推箱子游戏，设计巧妙，值得一看。
vc++经典的仿3D的推箱子游戏，设计巧妙，值得一看。-vc++ classic imitation of Sokoban 3D games, so cleverly designed and worth a visit.
- 2023-08-11 09:15:05下载
- 积分：1
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LPC3250的U
LPC3250 u-boot和linux内核的移植。-LPC3250 u-boot and linux kernel transplant.
- 2023-01-10 17:10:03下载
- 积分：1
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好书，项目管理基本概念
好书，项目管理基本概念-books, the basic concepts of project management
- 2023-06-18 18:05:05下载
- 积分：1
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seed xdb560 usb
seed xdb560 usb安装说明-seed xdb560 usb
- 2022-05-22 06:14:23下载
- 积分：1
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Serial development of a good book on the serial port control, programming and th...
很好的串口开发的电子书 关于串口控件编程以及CSerialPort类的使用与开发！-Serial development of a good book on the serial port control, programming and the use and development of CSerialPort class!
- 2022-01-23 10:32:50下载
- 积分：1
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The_C_Programming_Language__2nd_Edition.part 4
The_C_Programming_Language__2nd_Edition.part 4
- 2023-05-04 18:40:03下载
- 积分：1
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FPGA pipelined designs on paper This work investigates the use of very deep pipe...
关于FPGA流水线设计的论文
This work investigates the use of very deep pipelines for
implementing circuits in FPGAs, where each pipeline
stage is limited to a single FPGA logic element (LE). The
architecture and VHDL design of a parameterized integer
array multiplier is presented and also an IEEE 754
compliant 32-bit floating-point multiplier. We show how to
write VHDL cells that implement such approach, and how
the array multiplier architecture was adapted. Synthesis
and simulation were performed for Altera Apex20KE
devices, although the VHDL code should be portable to
other devices. For this family, a 16 bit integer multiplier
achieves a frequency of 266MHz, while the floating point
unit reaches 235MHz, performing 235 MFLOPS in an
FPGA. Additional cells are inserted to synchronize data,
what imposes significant area penalties. This and other
considerations to apply the technique in real designs are
also addressed.-FPGA pipelined designs on paper This work invest
- 2022-11-28 12:05:03下载
- 积分：1
