-
softdemodulation-of-8psk
讲述软解调很不错的一片文档，主要阐述的是8PSK的软解调FPGA实现，但对8PSK的软解调原理阐述很清楚，没有多余的东西，但需要注意其中各个调制符号点得顺序。(About soft demodulation of a document is very good, mainly on the soft 8PSK demodulation FPGA, but soft 8PSK demodulation principle describes very clearly, no extra stuff, but need to pay attention to the point where each modulation symbol was in order.)
- 2014-06-03 14:12:05下载
- 积分：1
-
4
说明： document qpsk vhdl code
- 2018-01-06 09:27:04下载
- 积分：1
-
clock
软件开发环境：ISE 7.1i 仿真环境：ModelSim SE 6.0 1. 多功能数字钟(Software development environment: ISE 7.1i simulation environment: ModelSim SE 6.0 1. Multi-function digital clock)
- 2009-03-22 12:44:34下载
- 积分：1
-
卡内基梅陇大学verilog课程讲义-unlocked
verilog讲义
卡内基梅陇大学verilog课程讲义-unlocked
卡内基梅陇大学verilog课程讲义-unlocked(Verilog Course Lectures at Carnegie Mellon, University Verilog Course Lectures at Carnegie Mellon University Verilog Course Lectures at Carnegie Mellon University)
- 2020-06-20 18:00:02下载
- 积分：1
-
Verilog版的C51核(DW8051)
Verilog版的C51核(DW8051)-Verilog version of the C51 core (DW8051)
- 2022-02-27 07:41:54下载
- 积分：1
-
ytupn
Very suitable for the study using computer vision, Analysis of the signal time domain, frequency domain, cepstrum, cyclic spectrum, etc. The performance of the program has reached a high level.
- 2017-09-02 18:07:13下载
- 积分：1
-
//led.v
/*
//led.v
/*-------------------------------------
LED显示模块：led(CLK,AF,ADDR,DATA)
功能： 显示
注意事项： 8位LED
参数： CLK:扫妙时钟输入，推荐1kHz
AF:数码管输出，a～h
ADDR:数码管选择位数出，0~2
DATA:显示数据输入0~9999 9999
编写人： 黄道斌
编写日期： 2006/07/13
-------------------------------------*/-//led.v /*------------------------------------- LED Display Module : led (CLK, AF, ADDR. DATA) function : to show : 8 LED parameters : CLK : So Wonderful clock input, Suggest 1kHz AF : digital tube output, a ~ h ADDR : digital control options from the median, 0 ~ 2 DATA : data show that the importation of 0 ~ 9999 9999 prepared : Huang Daobin preparation date : 2006/07/13-------------------------------------*/
- 2022-06-03 00:26:09下载
- 积分：1
-
(Oxford)-Computer-Arithmetic--Algorithms-a-Hardwa
Computer Arithmetic (press 2000)
- 2012-01-27 09:45:29下载
- 积分：1
-
baseband_verilog
verilog实现的基带信号编码，整个系统分为六个模块，分别为：时钟模块,待发射模块,卷积模块,扩频模块,极性变换和内插模块,成型滤波器(verilog implementation baseband signal coding, the entire system is divided into six modules, namely: the clock module, to be launched modules, convolution module, spread spectrum modules, polarity transform and interpolation modules, forming filter)
- 2009-10-08 10:19:34下载
- 积分：1
-
Read_SPI_ADC
This VHDL code takes a clock, reset, Capture_EN and SPI data LT2315 ADC and generates SPI_CLK and SPI_nCS of it and reads 12-bit serial data ADC and returns 12-bit parallel data.
- 2015-10-13 14:43:13下载
- 积分：1
