-
SOS
使用matlab生成SOS滤波器，应用于FPGA的一个小型系统，有一定的参考价值(Using MATLAB to generate SOS filter, applied to a small system of FPGA, there is a certain reference value)
- 2016-07-31 20:53:19下载
- 积分：1
-
Ping_pong_Sparten3e-master
FPGA实现乒乓球游戏 代码及仿真 VGA实现(FPGA realizes table tennis game code and simulation VGA implementation)
- 2019-05-06 20:22:13下载
- 积分：1
-
DDS signal generator, can produce a variety of waveforms, are mysterious wave, t...
DDS信号发生器，能产生多种波形，正玄波，三角波，方波，频率可调，相位可调-DDS signal generator, can produce a variety of waveforms, are mysterious wave, triangle wave, square wave, frequency tunable, phase adjustable
- 2022-11-28 01:05:04下载
- 积分：1
-
16QAM
说明： 在quartus上运行16QAM仿真，实现在modelsim上的波形仿真(Running 16QAM simulation on quartus)
- 2020-04-27 18:24:11下载
- 积分：1
-
- 2022-01-31 01:25:48下载
- 积分：1
-
Nios_Example_07_SD_35TFT
这是一个nios工程，控制TFT液晶屏的程序。FPGA平台用Verilog HDL语言编写的，MCU软核程序有C语言编写。通过这一个完成的工程，你就会明白SOPC的一些实现方法。(This is a nios engineering, control TFT LCD screen program. The FPGA platform Verilog HDL language preparation with the nuclear program has a soft, MCU written in C language. Through this a complete project, you will understand some of the SOPC methods of realization.
)
- 2011-05-24 16:56:27下载
- 积分：1
-
Commonly used phase
常用的锁相环技术，此程序是我在设计高频电路中运用的，具体见程序，经调试无问题-Commonly used phase-locked loop technology, this program is in the design I used in high-frequency circuits, see the specific procedures, no problem by debugging
- 2022-10-15 08:30:03下载
- 积分：1
-
本程序使用vhdl编写的jtag接口实现程序,其中有些功能未能实现,希望有人能够帮忙完善!
本程序使用vhdl编写的jtag接口实现程序,其中有些功能未能实现,希望有人能够帮忙完善!-vhdl the procedures used to prepare the jtag interface procedures, which some of them did not materialize, hope someone can help perfect!
- 2022-03-01 07:15:01下载
- 积分：1
-
verilog编写的流水线模块
verilog编写的流水线模块-Verilog modules prepared by the Pipeline
- 2022-03-30 09:04:46下载
- 积分：1
-
FIFO
This is a simple example of FIFO(first in and first out) module written in verilog code(This is a simple example of FIFO (first in and first out) module written in verilog code)
- 2013-10-04 00:41:42下载
- 积分：1
