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参考例子_收发ASM
参考例子_收发ASM-1-reference example _ TX ASM-1
- 2022-11-01 21:30:03下载
- 积分：1
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arm9200 the development of manuals about how to ARM9200 and LINUX in the applica...
arm9200的开发手册，讲述了怎么样在ARM9200和LINUX下开发应用系统 。-arm9200 the development of manuals about how to ARM9200 and LINUX in the application system under development.
- 2022-03-26 18:01:02下载
- 积分：1
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电机转速计
测量采用 AVR 单片机泰文 16 的电机转速。使用 2 x 16 个字符离型 crytial 显示器显示。
从通过中断一个光电传感器的输入的信号。
- 2023-01-02 05:35:53下载
- 积分：1
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可以在三星的ARM处理器s3c44b0上移植的bootLoader源代码
可以在三星的ARM处理器s3c44b0上移植的bootLoader源代码-in Samsung ARM processor s3c44b0 transplant bootLoader on source code
- 2022-12-16 17:50:03下载
- 积分：1
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ARM7开发源码，源码要求为至少5个C或Java源码，质量越高得到的下载个数越多(一般为200:上载5个，可以下载200个)。...
ARM7开发源码，源码要求为至少5个C或Java源码，质量越高得到的下载个数越多(一般为200:上载5个，可以下载200个)。-ARM7，hello world,I love c++,so if I want to ..........
- 2022-07-05 03:13:57下载
- 积分：1
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1T51单片机实现精确数字钟 因为普通单片机内核是12T 这里采用1T51内核的使得定时误差变得极小，同时加入补偿函数可以说定时已经达到理想精度...
1T51单片机实现精确数字钟 因为普通单片机内核是12T 这里采用1T51内核的使得定时误差变得极小，同时加入补偿函数可以说定时已经达到理想精度-1T51 SCM accurate digital clock for the general microcontroller core is used here 1T51 core 12T makes timing error becomes minimal, while adding compensation function can be said to have been from time to time to achieve the desired accuracy
- 2022-08-12 08:37:06下载
- 积分：1
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Their board in 16 experiments conducted successful experiments in a very good nu...
自己在16实验板上实验成功的几个16实验程序非常好的-Their board in 16 experiments conducted successful experiments in a very good number of 16 experimental procedure
- 2022-02-05 12:25:30下载
- 积分：1
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an operating system source code
一个操作系统的源码-an operating system source code
- 2022-04-20 14:32:55下载
- 积分：1
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8位crc校验的计算源码,查表计算,可以计算任意8位的多项式的校验...
8位crc校验的计算源码,查表计算,可以计算任意8位的多项式的校验-8 bit CRC compute program.
- 2022-03-12 19:29:19下载
- 积分：1
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A Tiny Microcontroller for FPGAs
应用背景Abstract—Leros is a tiny microcontroller that is optimized for
current low-cost FPGAs. Leros is designed with a balanced logic
to on-chip memory relation. The design goal is a microcontroller
that can be clocked in about half of the speed a pipelined on-chip
memory and consuming less than 300 logic cells.
The architecture, which follows from the design goals, is a
pipelined 16-bit accumulator processor. An implementation of
Leros needs at least one on-chip memory block and a few hundred
logic cells.
The application areas of Leros are twofold: First, it can be used
as an intelligent peripheral device for auxiliary functions in an
FPGA based system-on-chip design. Second, the very small size
of Leros makes it an attractive softcore for many-core research
with low-cost FPGAs.关键技术The smallest core is comparable to Leros and can be implemented
- 2023-09-03 01:00:04下载
- 积分：1
