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8层电梯FPGA控制系统
基于FPGA XILINX平台实现8层电梯的控制系统设计,编程语言为verilog,IDE平台为VIVADO。
该代码实用,可以提供参考。系统采用模块化设计,方便代码移植、集成,代码的激励文件测试需要自己编写一下,比较简单
- 2022-02-01 05:17:29下载
- 积分:1
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8-解码器 FPGA
8 位解码器使用 verliog,fpga,使用 verliog,fpga,使用 verliog,fpga,使用 verliog,fpga,使用 verliog,fpga,使用 verliog,fpga,使用 verliog,fpga,使用 verliog 的8 位解码器上的 led 指示灯的8 位解码器上的 led 指示灯的8 位解码器上的 led 指示灯的8 位解码器上的 led 指示灯的8 位解码器上的 led 指示灯的8 位解码器上的 led 指示灯的8 位解码器上的 led 指示灯fpga, 8 位解码器使用 verliog,fpga 上的 led 指示灯上的 led 指示灯
- 2022-08-17 17:49:44下载
- 积分:1
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hamid
very nice program that i ensure anyone can use easily and will be efficient for hard project of elevator
- 2009-07-26 13:27:38下载
- 积分:1
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verilog fifo 代码
FIFO is a First-In-First-Out memory queue with control logic that manages
the read and write operations, generates status flags, and provides optional
handshake signals for interfacing with the user logic. It is often used to
control the flow of data between source and destination. FIFO can be
classified as synchronous or asynchronous depending on whether same clock
or different (asynchronous) clocks control the read and write operations. In
this project the objective is to design, verify and synthesize a synchronous
FIFO using binary coded read and write pointers to address the memory
array. FFIO full and empty flags are generated and passed on to source and
destination logics, respectively, to pre-empt any overflow or underflow of
data. In this way data integrity between source and destination is maintained.
The RTL description for the FIFO is
- 2022-05-22 08:44:13下载
- 积分:1
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FPGA的I2S接收模块 audio_in_buff
说明: 用于FPGA的I2S接收模块,仅供学习和参考(audio-i2s receive.use fpga.)
- 2019-04-21 12:11:23下载
- 积分:1
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encode_64_66
自编的64B/66B编码程序,下次上传解码程序。(the 64B/66B coding process is written by myself, i will upload the decoding process next time.)
- 2011-08-27 10:38:53下载
- 积分:1
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Verilog DDS发生器的实现
一个从0-1MHZ的正弦DDS发生器,如果你对Verilog语言以及FPGA有兴趣的话,这个可以作为一个入门的教程。有兴趣的朋友们可以来下载,如果有什么不懂的地方可以随时请教楼主,如果代码中有什么问题的话,也可以向楼主提出改正。
- 2022-05-27 11:34:39下载
- 积分:1
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VHDL-Keyboard
设计制作一个检测4*4矩阵键盘的按键编码的实验,把实际按键的键值的八位编码先转换成从0000—1111的编码,再译成数码管能识别的八位编码,在数码管动态显示时,4*4矩阵键盘的第一行对应00—03,第二行对应04—07,第三行08—11,第四行对应12—15。(Design a 4* 4 matrix keyboard key coding experiments to detect the key the actual key octet coded first convert from 0000-1111 encoding, and then translated into digital tube to identify the eight coding, digital tube dynamic display, the first line of the 4* 4 matrix keyboard corresponding to 00-03, the second line corresponds to 04-07, the third line of 08-11, the fourth line corresponds to 12-15.)
- 2012-07-01 10:02:33下载
- 积分:1
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bcdadd
4-Bit BCD Adder in Verilog
- 2014-03-26 09:29:21下载
- 积分:1
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试验台的 cavlc entrope 解码器
描述
- 2022-01-23 10:08:11下载
- 积分:1