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Verilog HDL

于 2023-03-01 发布文件大小:3.31 kB

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hdb3_v3
Quartus环境下使用Verilog编写的HDB3编解码程序，RTL和时序仿真已过(Quartus under the environment of a HDB3 protocol procedures written in Verilog, RTL and timing simulation has be passed)

2015-11-24 21:56:05下载

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verilog 温度控制命令
verilog 温度控制命令实现了温度的采集和运算，以及其他控制命令很好哦

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积分：1
lab_instructions3
The objective of the labs today is to give you a basic understanding of FPGA design and enough experience to begin your own FPGA design with the ISE 10.1 tools and the Xilinx Spartan-3A DSP 1800A Starter Kit.

2010-12-31 17:16:42下载

积分：1
data_swith
verilog 代码实现串并转换，有延迟(Verilog code and string conversion, delay)

2011-07-31 23:58:17下载

积分：1
nfc
近场通信的verilog描述，包含向量名定义，顶层设计等等的精确描述(Verilog description of near field communication, including the vector name is defined, an accurate description of the top-level design, etc.)

2015-08-11 15:27:41下载

积分：1
fft1024 verilog代码
fft1024 verilog 代码可以编译成功建议下载学习(The fft1024 verilog code can compile successful Suggestions for download learning)

2017-07-20 10:31:05下载

积分：1
flash_test_24
说明：实现fpga 读写flash 在k7上验证(Realization of FPGA read-write flash verification on K7)

2020-06-18 20:00:02下载

积分：1
CRC _ Verilog 16
vivado工程下的Verilog语言的CRC_16,并行输入任意字节长度，均可求出来，数据的校验码，代码给的是512个字节宽度的数据源，长度可以自行修改，亲测实际工程~~~

2022-01-29 03:28:35下载

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add_noisem
把指定的噪声叠加到信号上去.有标准噪声库NOISEX-92，其中带有白噪声、办公室噪声、工厂噪声、汽车噪声、坦克噪声等等，在信号处理中往往需要把库中的噪声叠加到信号中去，而噪声的采样频率与纯信号的采样频率往往不一致，需要采样频率的校准。 (The specified noise superimposed to the signal up. Standard noise library NOISEX-92, with white noise, office noise, factory noise, car noise, tank noise in the signal processing often requires noise to be superimposed in the library The signal to noise of the sampling frequency and pure signal sampling frequency is often inconsistent sampling frequency of calibration.)

2012-08-10 14:18:33下载

积分：1
iic程序
这是IIc才程序，验证完成，可以直接复用，不许更改，有详细的文档介绍，和对应的代码

2022-11-19 11:00:03下载

积分：1

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Verilog HDL

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